Patents by Inventor Kyouichi KASHIMA

Kyouichi KASHIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 9136717
    Abstract: A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 15, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyouichi Kashima, Yoshitaka Fukushima, Masahiro Ono, Tetsuro Hirano
  • SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20110235224
    Abstract: A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 29, 2011
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Kyouichi KASHIMA, Yoshitaka Fukushima, Masahiro Ono, Tetsuro Hirano