Patents by Inventor Kyouji Yoshino
Kyouji Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8671126Abstract: Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1?D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7.Type: GrantFiled: November 2, 2010Date of Patent: March 11, 2014Assignee: DAI Nippon Printing Co., Ltd.Inventors: Motonobu Tonomura, Kyouji Yoshino
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Patent number: 8265427Abstract: Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1?D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7.Type: GrantFiled: November 2, 2010Date of Patent: September 11, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Motonobu Tonomura, Kyouji Yoshino
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Patent number: 8000563Abstract: An interpolation process for scaling is performed directly on raw data from an image pickup apparatus. Raw data, constituted by inputted Bayer pattern array are as a set of pixels positioned on respective lattice points on a square lattice. A position of an interpolation point Q is designated by an upper address that indicates a lattice point near the upper left and a lower address that indicates a position inside a lattice frame, a specific color is designated for which a pixel value is to be determined. An interpolation reference frame is determined, formed of a smallest square, which contains the interpolation point Q and with which the four vertices are formed by lattice points of the designated color, and an interpolation origin, constituted by the upper left lattice point of the interpolation reference frame, interpolation proportions d* and e* are determined. An interpolation calculation is performed.Type: GrantFiled: August 9, 2007Date of Patent: August 16, 2011Assignee: Dai Nippon Printing Co., Ltd.Inventors: Kyouji Yoshino, Motonobu Tonomura, Hajime Seino
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Publication number: 20110055304Abstract: Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1?D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7.Type: ApplicationFiled: November 2, 2010Publication date: March 3, 2011Inventors: Motonobu TONOMURA, Kyouji Yoshino
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Publication number: 20110044562Abstract: Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1?D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7.Type: ApplicationFiled: November 2, 2010Publication date: February 24, 2011Inventors: Motonobu TONOMURA, Kyouji Yoshino
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Patent number: 7840623Abstract: Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1?D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7.Type: GrantFiled: September 19, 2006Date of Patent: November 23, 2010Assignee: Dai Nippon Printing Co., Ltd.Inventors: Motonobu Tonomura, Kyouji Yoshino
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Publication number: 20080056618Abstract: An interpolation process for scaling is performed directly on raw data from an image pickup apparatus. Raw data, constituted of Bayer pattern array pixels input by a pixel value input unit 110 are stored in a pixel value storage unit 120 as a set of pixels positioned on respective lattice points on a square lattice. An interpolation point designating unit 170 designates a position of an interpolation point Q by an upper address that indicates a lattice point near the upper left and a lower address that indicates a position inside a lattice frame, and a calculation target color designating unit 160 designates a specific color for which a pixel value is to be determined.Type: ApplicationFiled: August 9, 2007Publication date: March 6, 2008Inventors: Kyouji Yoshino, Motonobu Tonomura, Hajime Seino
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Publication number: 20070136409Abstract: Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1?D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7.Type: ApplicationFiled: September 19, 2006Publication date: June 14, 2007Inventors: Motonobu Tonomura, Kyouji Yoshino