Abstract: A storage device including: a nonvolatile memory device including a first, second and third area; and a controller to receive a first write command including a first logical block address from a host, to receive first data corresponding to the first logical block address in response to the first write command, and store the first data in the nonvolatile memory device, when the first write command includes area information, the controller stores the first data in the first area or the second area based on the area information, when the first write command does not include the area information, the controller stores the first data in the third area, each of the first area and the second area includes memory cells each storing “n” bits (n being a positive integer), and the third area includes memory cells each storing “m” bits (m being a positive integer greater than n).

Abstract: A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.

Abstract: A storage device includes a nonvolatile memory device that includes a first region including memory cells configured to store n-bit data and a second region including memory cells configured to store m-bit data and a memory controller, where n and m are natural numbers and n is less than m. The first region includes a first area and a second area, and the second region includes a third area. The memory controller is configured to perform one of a turbo write operation on the first area or the second area and a normal write operation on the third area, and configured to perform one of a turbo read operation on the first area or the second area and a normal read operation on the third area.

Abstract: A storage device includes a descramble module configured to descramble at least a portion of a read command, which includes logical block address (LBA) information and first meta information, into first signature information and first physical address (PA) information, for accessing a flash memory. A compare module is provided, which is configured to compare the first signature information against stored signature information to thereby determine an equivalency or discrepancy therebetween. An access module is provided, which is configured to use the first PA information to access a data region of the flash memory, upon determination of the equivalency by said compare module.

Abstract: An input/output (I/O) scheduling device comprises a plurality of trans-descriptor operators each corresponding to one of a plurality of hosts and configured to sustain a trans-descriptor and transmit the trans-descriptor to a hardware module, a transmitting scheduler configured to schedule transmission of trans-descriptors through communication with the plurality of trans-descriptor operators, and a receiving scheduler configured to schedule reception of trans-descriptors through communication with the trans-descriptor operators.

Abstract: An input/output (I/O) scheduling device comprises a plurality of trans-descriptor operators each corresponding to one of a plurality of hosts and configured to sustain a trans-descriptor and transmit the trans-descriptor to a hardware module, a transmitting scheduler configured to schedule transmission of trans-descriptors through communication with the plurality of trans-descriptor operators, and a receiving scheduler configured to schedule reception of trans-descriptors through communication with the trans-descriptor operators.

Abstract: A controller for processing a command in a data storage device includes at least one bitmap and a firmware command que. The at least one bitmap is formed in hardware to indicate that the command is received. The firmware command que is generated by firmware for storing the command when the at least one bitmap indicates receipt of the command. The firmware generates the firmware command que that is of variable size for processing a high number of commands. In addition, the bitmaps are generated in the hardware for quickly receiving the high number of commands.

Abstract: A controller for processing a command in a data storage device includes at least one bitmap and a firmware command queue. The at least one bitmap is formed in hardware to indicate that the command is received. The firmware command queue is generated by firmware for storing the command when the at least one bitmap indicates receipt of the command. The firmware generates the firmware command queue that is of variable size for processing a high number of commands. In addition, the bitmaps are generated in the hardware for quickly receiving the high number of commands.