Abstract: A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.

Abstract: An output circuit receives a data signal biased within a first voltage range associated with a first power supply voltage and generates an output signal on an output node biased within a second voltage range in response to the data signal, the second voltage range is associated with a second power supply voltage greater than the first power supply voltage. The output circuit generates pull-up and pull-down signals that are within the first voltage range in response to the data signal. The output circuit includes an output driver circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit, when activated, generates the output signal indicative of the second power supply voltage in response to a modified pull-up signal being the pull-up signal level-shifted to a third voltage range. The pull-down circuit, when activated, generates the output signal being the ground potential in response to the pull-down signal.

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCl).

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

Abstract: A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is being read out. In this manner, the read speed for the sequential read operation of the flash memory device is improved. In some embodiments, the memory cell array for each input-output (I/O) of the flash memory device is partitioned into two sub-banks to further reduce the read cycle time by enabling early activation of the word-line for the next sub-bank.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.

Abstract: A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.

Abstract: A non-volatile memory device includes a control circuit configured to perform a block erase operation including a block erase cycle and an erase verify cycle on a block of memory cells. The control circuit is configured to perform the erase verify cycle by storing a last verify address for each sector of the block of memory cells, verifying each memory cell in a sector starting from the last verify address for the sector until a memory cell has failed erase verification in that sector, storing the memory cell address of the failed memory cell as the last verify address for that sector, skipping the erase verification for the remaining memory cells in that sector, and continuing the erase verify cycle at a last verify address for the next sector.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.

Abstract: A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.

Abstract: A method to trim a reference voltage source formed on an integrated circuit includes configuring the integrated circuit in a test mode; providing a power supply voltage and a trim code sequence to the integrated circuit where the power supply voltage is provided by a precision reference voltage source; generating a target voltage on the integrated circuit using the power supply voltage; generate a reference voltage using the reference voltage source formed on the integrated circuit; applying one or more trim codes in the trim code sequence to the reference voltage source to adjust the reference voltage; comparing the reference voltage generated based on the trim codes to the target voltage; asserting a latch signal in response to a determination that the reference voltage generated based on a first trim code is equal to the target voltage; and storing the first trim code in response to the latch signal being asserted.

Abstract: A memory apparatus includes a main memory, a redundant memory, and a substitution control unit. The main memory is configured to receive a read address and output a main data word comprising a plurality of main data sub-words where the read address includes a first portion and a second portion. The redundant memory is configured to receive the read address first portion and output a redundant data sub-word. The substitution control unit includes a substitution control word memory configured to store a plurality of substitution control words and configured to receive the read address first portion and assert a substitution control word including a substitution address second portion. The read address first portion and substitution address second portion form a substitution address. The substitution control unit asserts a substitution control signal when there is a match between the read address and the substitution address.

Abstract: A memory apparatus includes a main memory, a redundant memory, and a substitution control unit. The main memory is configured to receive a read address and output a main data word comprising a plurality of main data sub-words where the read address includes a first portion and a second portion. The redundant memory is configured to receive the read address first portion and output a redundant data sub-word. The substitution control unit includes a substitution control word memory configured to store a plurality of substitution control words and configured to receive the read address first portion and assert a substitution control word including a substitution address second portion. The read address first portion and substitution address second portion form a substitution address. The substitution control unit asserts a substitution control signal when there is a match between the read address and the substitution address.

Abstract: A sense amplifier circuit includes a latch circuit to enhance the speed of a sensing operation and to obviate the need for a latch circuit to capture the output value of the sense amplifier circuit. In one embodiment, first and second differential amplifiers provide a differential signal to the latch circuit. The high gain in the latch circuit resolves the differential signal to a logic signal, which is then provided to an output amplifier. In one embodiment, the differential signal is provided to the latch circuit after the differential signal across the input terminals of the first and second differential amplifiers exceeds a predetermined value.

Abstract: A sense amplifier circuit includes a latch circuit to enhance the speed of a sensing operation and to obviate the need for a latch circuit to capture the output value of the sense amplifier circuit. In one embodiment, first and second differential amplifiers provide a differential signal to the latch circuit. The high gain in the latch circuit resolves the differential signal to a logic signal, which is then provided to an output amplifier. In one embodiment, the differential signal is provided to the latch circuit after the differential signal across the input terminals of the first and second differential amplifiers exceeds a predetermined value.

Abstract: This invention diecloses a negative charge pump comprises a negative charge pump comprises; a positive charge pump to output a positive voltage through a first output terminal in response to a first clock signal and a second clock signal; a transfer circuit having a second output terminal, in which the transfer circuit acts to transfer the positive voltage to the second output terminal or break the positive voltage in response to a third clock signal; a negative charge pump circuit having a third output terminal which maintains a first potential during the second output terminal maintains the positive voltage or maintains a second potential in response to a fourth clock signal during the positive voltage is not supplied to the second output terminal; and an output circuit having a fourth output terminal, in which the output circuit acts to charge positive charges which exist in an external equipment to the third output terminal through the fourth output terminal when the first potential changes to the second

Abstract: The present invention is to provide to a charge pumping circuit capable of reducing the area of the layout by making the positive and negative charge pump in a single circuit, of enhancing the efficiency of the pump and of making the pumping speed high with the high driving voltage. The charge pumping circuit comprises: a charge pump for generating voltage amplitude which is over Vdd; a positive charge pump for transferring positive charges from the charge pump in response to a first control signal; a negative charge pump for transferring negative charges from the charge pump in response to the first control signal; and a controller for making a voltage, which is applied to the negative charge pump, to a ground voltage level at a negative charge operation, and for providing a voltage level for the negative charge pump to prevent charges from flowing to the negative charge pump.