Patents by Inventor Kyoung-Eun Chang

Kyoung-Eun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11217709
    Abstract: In a graphene-semiconductor heterojunction photodetector and a method of manufacturing the same according to the present inventive concept, a source electrode and a test electrode are formed to face each other on a graphene layer, and a drain electrode is formed in a direction perpendicular to a central region portion of the graphene layer, so that the drain electrode may be physically separated from the graphene layer. Further, charges formed at the central region portion of the graphene layer are transmitted to the drain electrode through a substrate, so that high photosensitivity may be secured, and a high output voltage may be secured for the applied light. Accordingly, the drain electrode is formed at a side surface of the graphene layer, so that the size of the drain electrode may be easily controlled, and a high output voltage may be obtained.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 4, 2022
    Inventors: Byoung Hun Lee, Kyoung Eun Chang
  • Publication number: 20200350443
    Abstract: In a graphene-semiconductor heterojunction photodetector and a method of manufacturing the same according to the present inventive concept, a source electrode and a test electrode are formed to face each other on a graphene layer, and a drain electrode is formed in a direction perpendicular to a central region portion of the graphene layer, so that the drain electrode may be physically separated from the graphene layer. Further, charges formed at the central region portion of the graphene layer are transmitted to the drain electrode through a substrate, so that high photosensitivity may be secured, and a high output voltage may be secured for the applied light. Accordingly, the drain electrode is formed at a side surface of the graphene layer, so that the size of the drain electrode may be easily controlled, and a high output voltage may be obtained.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Byoung Hun LEE, Kyoung Eun CHANG
  • Publication number: 20170256667
    Abstract: Disclosed herein is a photodetector utilizing graphene. A single-layer graphene channel is formed on a semiconductor substrate doped with n-type impurity. The graphene channel has an end connected to a source electrode and is physically separated from a drain electrode. Light having passed through a gate insulation layer and a gate electrode generates electron-hole pairs at the interface between the graphene channel and the semiconductor substrate forming a Schottky junction, and a photocurrent is generated by a Schottky barrier. In addition, the Schottky barrier is changed according to an applied gate voltage, thereby changing the photocurrent.
    Type: Application
    Filed: February 23, 2017
    Publication date: September 7, 2017
    Inventors: Byoung Hoon LEE, Kyoung Eun CHANG, Tae Jin YOO, Hyeon Jun HWANG
  • Publication number: 20160181159
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Sung-Jin WHANG, Moon-Sig JOO, Yong-Seok EUN, Kwon HONG, Bo-Min SEO, Kyoung-Eun CHANG, Seung-Woo SHIN
  • Patent number: 9293337
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang
  • Patent number: 9275904
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 1, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Yong-Seok Eun, Kwon Hong, Bo-Min Seo, Kyoung-Eun Chang, Seung-Woo Shin
  • Publication number: 20140370702
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Sung-Jin WHANG, Moon-Sig JOO, Kwon HONG, Jung-Yeon LIM, Won-Kyu KIM, Bo-Min SEO, Kyoung-Eun CHANG
  • Patent number: 8847300
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: September 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang
  • Publication number: 20110045666
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Application
    Filed: November 9, 2009
    Publication date: February 24, 2011
    Inventors: Sung-Jin WHANG, Moon-Sig Joo, Yong-Seok Eun, Kwon Hong, Bo-Min Seo, Kyoung-Eun Chang, Seung-Woo Shin
  • Publication number: 20100283096
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Application
    Filed: December 17, 2009
    Publication date: November 11, 2010
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang