Abstract: A memory device that supports a built-in self-test (BIST) operation includes: a plurality of memory cells; a page buffer group including page buffer circuits respectively coupled to the plurality of memory cells through bit lines; a built-in self-test (BIST) controller configured to generate pattern data to be stored in the page buffer circuits and reference data to be compared with sensed data obtained from the page buffer circuits, and to compare the reference data with the sensed data; and an input/output control circuit configured to input the pattern data to the page buffer circuits and to transfer the sensed data from the page buffer circuits to the BIST controller.

Abstract: A memory device that supports a built-in self-test (BIST) operation includes: a plurality of memory cells; a page buffer group including page buffer circuits respectively coupled to the plurality of memory cells through bit lines; a built-in self-test (BIST) controller configured to generate pattern data to be stored in the page buffer circuits and reference data to be compared with sensed data obtained from the page buffer circuits, and to compare the reference data with the sensed data; and an input/output control circuit configured to input the pattern data to the page buffer circuits and to transfer the sensed data from the page buffer circuits to the BIST controller.

Abstract: According to an embodiment, a storage device may be provided. The storage device may include a semiconductor memory device, and a memory controller configured for controlling the semiconductor memory device. The semiconductor memory device may include a memory unit including a plurality of memory chips. The semiconductor memory device may include an interface chip realigning serial data received from the memory controller into parallel data and transferring the parallel data to each of the plurality of memory chips.

Abstract: According to an embodiment, a storage device may be provided. The storage device may include a semiconductor memory device, and a memory controller configured for controlling the semiconductor memory device. The semiconductor memory device may include a memory unit including a plurality of memory chips. The semiconductor memory device may include an interface chip realigning serial data received from the memory controller into parallel data and transferring the parallel data to each of the plurality of memory chips.

Abstract: A differential amplification circuit may include a differential amplification unit including a first input transistor and a second input transistor, and suitable for differentially amplifying input signals inputted through the first and second input transistors; a first input control section suitable for turning off the first input transistor when the differential amplification circuit is disabled and transferring a first input signal to the first input transistor when the differential amplification circuit is enabled; and a second input control section suitable for turning off the second input transistor when the differential amplification circuit is disabled and transferring a second input signal to the second input transistor when the differential amplification circuit is enabled.

Abstract: A transmitting/receiving system may include a transmitting circuit and a receiving circuit. The transmitting circuit may include: a pull-up element suitable for pull-up driving a first node in response to a signal; a pull-down element suitable for pull-down driving a second node in response to the signal; and a voltage tailor coupled between the first and second nodes, and transmitting a low-swing signal obtained by reducing the swing amplitude of the signal to a transmission line, and the receiving circuit may include: a reference voltage generator having a replica circuit of the receiving circuit and suitable for generating a reference voltage; and a differential amplifier suitable for differentially amplifying the reference voltage and the low-swing signal received through the transmission line.

Abstract: Disclosed are a differential amplifier circuit and a semiconductor memory device including the same, wherein the differential amplification circuit includes: a differential amplifier activated in response to an enable signal, capable of differentially amplifying input signals inputted through input terminals and outputting output signals; and an operation control section capable of sequentially applying signals having a voltage difference increasing in stepped fashion to the input terminals of the differential amplifier, measuring voltages of the output signals of the differential amplifier to detect an input offset, and adjusting an activation timing of the enable signal depending on a detected offset.

Abstract: A differential amplification circuit may include a differential amplification unit including a first input transistor and a second input transistor, and suitable for differentially amplifying input signals inputted through the first and second input transistors; a first input control section suitable for turning off the first input transistor when the differential amplification circuit is disabled and transferring a first input signal to the first input transistor when the differential amplification circuit is enabled; and a second input control section suitable for turning off the second input transistor when the differential amplification circuit is disabled and transferring a second input signal to the second input transistor when the differential amplification circuit is enabled.

Abstract: A transmitting/receiving system may include a transmitting circuit and a receiving circuit. The transmitting circuit may include: a pull-up element suitable for pull-up driving a first node in response to a signal; a pull-down element suitable for pull-down driving a second node in response to the signal; and a voltage tailor coupled between the first and second nodes, and transmitting a low-swing signal obtained by reducing the swing amplitude of the signal to a transmission line, and the receiving circuit may include: a reference voltage generator having a replica circuit of the receiving circuit and suitable for generating a reference voltage; and a differential amplifier suitable for differentially amplifying the reference voltage and the low-swing signal received through the transmission line.