Abstract: A display device includes a display panel including a first data line, a second data line, and a pixel, the pixel including a first sub-pixel coupled to the first data line, and a second sub-pixel coupled to the second data line, a light stress compensator configured to generate a first data voltage control signal for the first sub-pixel based on a second data value of input image data for the second sub-pixel, in response to a first data value of input image data for the first sub-pixel being equal to or less than a first reference value, and a data driver configured to generate a first data signal based on the first data value for the first sub-pixel, to provide a first data voltage to the first data line, and to vary the first data voltage based on the first data voltage control signal.

Abstract: A display device is disclosed that includes pixels, a memory, and a degradation compensator. The pixels include light emitting elements. The memory is operable to store degradation information including degradation degrees of the light emitting elements. The degradation compensator is operable to receive the degradation information and generate output grayscales by changing each of input grayscales of the pixels in proportion to each of the degradation degrees. The degradation compensator includes a degradation information changer for changing the degradation information by decreasing a degradation degree having a variation greater than a threshold value among variations of the degradation degrees.

Abstract: A display device includes a shift controller which generates an output image by shifting an input image within a shift range; and pixels which displays the output image. The shift controller sets the shift range to a first range when the input image is a moving image, and sets the shift range to a second range smaller than the first range when the input image is a still image.

Abstract: Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.

Abstract: Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.

Abstract: Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.

Abstract: Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.