Patents by Inventor Kyoung-hwan Park

Kyoung-hwan Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220204674
    Abstract: The present invention relates to a modified conjugated diene-based polymer having excellent processability and good tensile strength and viscoelasticity, and a rubber composition including the same, and provides a modified conjugated diene-based polymer including a first chain including a repeating unit derived from a conjugated diene-based monomer; a second chain including a repeating unit derived from a compound represented by Formula 1; and a derived unit from an alkoxysilane-based modifier, wherein the first chain and the second chain are coupled by the derived unit from the modifier.
    Type: Application
    Filed: September 11, 2020
    Publication date: June 30, 2022
    Applicant: LG Chem, Ltd.
    Inventors: Ho Young Lee, Jae Moon Jun, Jung Hwan Oh, Hye Jung Shin, Kyoung Hwan Oh, Hyun Jun Kim, Hyeon Jong Park
  • Publication number: 20220159855
    Abstract: A display apparatus including display panel, a rear case to cover a rear of the display panel and the rear case including a cable fixing hole to which a cable is fixed, a connector connected to the cable and fastened to the rear case so that the cable is connected to the rear case, a cable holder to surround a part of the cable and fixed to the cable fixing hole so that the cable is fixed to the rear case, and a clamp to fix the cable holder to the cable fixing hole, wherein the clamp includes a first hook to be fixed to the cable fixing hole, and a second hook having a different shape than a shape of the first hook and to be fixed to the cable fixing hole to have a greater fixing force than a fixing force of the first hook.
    Type: Application
    Filed: February 8, 2022
    Publication date: May 19, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Hun KIM, Kyoung Hwan KIM, Seong Soo KIM, Won Kyu PARK, Jin PARK, Kyeong Jae LEE, Byeong Kyu PARK
  • Publication number: 20220145066
    Abstract: An epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the epoxy resin composition, the epoxy resin composition including an epoxy resin; a curing agent; an inorganic filler; and a curing catalyst, the epoxy resin including an epoxy resin represented by Formula 1:
    Type: Application
    Filed: September 20, 2021
    Publication date: May 12, 2022
    Inventors: Yong Yeop PARK, Dong Hwan LEE, Kyoung Chul BAE, Min Joon SEO, Chul Ho LEE
  • Publication number: 20150143526
    Abstract: Provided is a control method of an access point controller (APC), the method including: (a) if occurrence of a predetermined security vulnerability checking event on particular terminal equipment is sensed, controlling the plurality of APs so that port scanning is capable of being performed on the particular terminal equipment; and (b) determining that security vulnerability has occurred in the particular terminal equipment in at least one of a case where the predetermined port is opened, a case where the predetermined port is closed, and a case where the number of opened ports exceeds a predetermined number, as a result of performing port scanning on the particular terminal equipment.
    Type: Application
    Filed: May 9, 2014
    Publication date: May 21, 2015
    Applicant: DAVOLINK INC.
    Inventors: Youn Geun JEON, Seong Ho JEON, Seung Ro JANG, Kyoung Hwan PARK
  • Patent number: 8908456
    Abstract: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Kyoung Hwan Park, Seung Won Kim
  • Publication number: 20130064029
    Abstract: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 14, 2013
    Applicant: SK HYNIX INC.
    Inventors: Kyoung Hwan PARK, Seung Won KIM
  • Patent number: 8338874
    Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Publication number: 20120217572
    Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.
    Type: Application
    Filed: May 11, 2012
    Publication date: August 30, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Patent number: 8203177
    Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: June 19, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Publication number: 20110204430
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
  • Patent number: 7955960
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
  • Patent number: 7867831
    Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Publication number: 20100308398
    Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.
    Type: Application
    Filed: August 17, 2010
    Publication date: December 9, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Patent number: 7799616
    Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: September 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Publication number: 20100190315
    Abstract: There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer.
    Type: Application
    Filed: November 5, 2009
    Publication date: July 29, 2010
    Inventors: Hack Seob SHIN, Kyoung Hwan Park
  • Patent number: 7629245
    Abstract: A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripheral region. A contact region of the capping layer is etched. A spacer is formed on sidewalls of the capping layer. A contact region of the blocking oxide layer is etched by using the spacer as a mask. The spacer is removed while etching a contact region of the trap nitride layer. A contact region of the tunneling layer is etched.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyoung Hwan Park
  • Publication number: 20090296476
    Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.
    Type: Application
    Filed: September 18, 2008
    Publication date: December 3, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
  • Patent number: 7616496
    Abstract: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun Seok Choi, Se Jun Kim, Kyoung Hwan Park, Hyun Seung Yoo
  • Publication number: 20080230830
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
  • Publication number: 20080225595
    Abstract: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.
    Type: Application
    Filed: June 29, 2007
    Publication date: September 18, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Eun Seok CHOI, Se Jun Kim, Kyoung Hwan Park, Hyun Seung Yoo