Patents by Inventor Kyoung-hwan Park
Kyoung-hwan Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240353593Abstract: Provided are an optical member and an optical display device comprising same, the optical member comprising a support layer and an optically functional layer laminated on one surface of the support layer, wherein: the optically functional layer includes a groove having inclined surfaces; at least one convex portion extending from the flat portion of the optically functional layer is formed at each of the inclined surfaces; the convex portion is a curved surface with a radius of curvature of 1 mm or greater, and each of the inclined surfaces satisfies expression 1.Type: ApplicationFiled: August 3, 2022Publication date: October 24, 2024Inventors: Kyoung Gon PARK, Sung Hyun MUN, Jin Young LEE, Ji Young HAN, Ji Won KANG, Ji Yeon KIM, Ji Ho KIM, Jae Hyun HAN, Il Jin KIM, Gwang Hwan LEE, Do Young KIM, Dong Myeong SHING
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Patent number: 12084605Abstract: An adhesive film formed of an adhesive composition including a (meth)acrylic copolymer including an alkylene glycol group and a cyclic functional group while satisfying Equation 3 and Equation 4 herein, an optical member including the same, and an optical display including the same, are provided.Type: GrantFiled: October 8, 2019Date of Patent: September 10, 2024Assignee: Samsung SDI Co., Ltd.Inventors: Ji Ho Kim, Ji Won Kang, Il Jin Kim, Sung Hyun Mun, Kyoung Gon Park, Gwang Hwan Lee, Jin Young Lee, Jae Hyun Han
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Patent number: 12066849Abstract: A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.Type: GrantFiled: May 13, 2022Date of Patent: August 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung Jun Roh, Jae Woo Park, Jun Han Choi, Myoung Bo Kwak, Jung Hwan Choi
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Patent number: 12069824Abstract: A display apparatus including display panel, a rear case to cover a rear of the display panel and the rear case including a cable fixing hole to which a cable is fixed, a connector connected to the cable and fastened to the rear case so that the cable is connected to the rear case, a cable holder to surround a part of the cable and fixed to the cable fixing hole so that the cable is fixed to the rear case, and a clamp to fix the cable holder to the cable fixing hole, wherein the clamp includes a first hook to be fixed to the cable fixing hole, and a second hook having a different shape than a shape of the first hook and to be fixed to the cable fixing hole to have a greater fixing force than a fixing force of the first hook.Type: GrantFiled: February 8, 2022Date of Patent: August 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Hun Kim, Kyoung Hwan Kim, Seong Soo Kim, Won Kyu Park, Jin Park, Kyeong Jae Lee, Byeong Kyu Park
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Publication number: 20150143526Abstract: Provided is a control method of an access point controller (APC), the method including: (a) if occurrence of a predetermined security vulnerability checking event on particular terminal equipment is sensed, controlling the plurality of APs so that port scanning is capable of being performed on the particular terminal equipment; and (b) determining that security vulnerability has occurred in the particular terminal equipment in at least one of a case where the predetermined port is opened, a case where the predetermined port is closed, and a case where the number of opened ports exceeds a predetermined number, as a result of performing port scanning on the particular terminal equipment.Type: ApplicationFiled: May 9, 2014Publication date: May 21, 2015Applicant: DAVOLINK INC.Inventors: Youn Geun JEON, Seong Ho JEON, Seung Ro JANG, Kyoung Hwan PARK
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Patent number: 8908456Abstract: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells.Type: GrantFiled: August 31, 2012Date of Patent: December 9, 2014Assignee: SK Hynix Inc.Inventors: Kyoung Hwan Park, Seung Won Kim
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Publication number: 20130064029Abstract: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells.Type: ApplicationFiled: August 31, 2012Publication date: March 14, 2013Applicant: SK HYNIX INC.Inventors: Kyoung Hwan PARK, Seung Won KIM
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Patent number: 8338874Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: GrantFiled: May 11, 2012Date of Patent: December 25, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Publication number: 20120217572Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: ApplicationFiled: May 11, 2012Publication date: August 30, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Patent number: 8203177Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: GrantFiled: August 17, 2010Date of Patent: June 19, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Publication number: 20110204430Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
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Patent number: 7955960Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: GrantFiled: March 21, 2008Date of Patent: June 7, 2011Assignee: Hynix Semiconductor Inc.Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
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Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack
Patent number: 7867831Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.Type: GrantFiled: September 18, 2008Date of Patent: January 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park -
Publication number: 20100308398Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: ApplicationFiled: August 17, 2010Publication date: December 9, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack
Patent number: 7799616Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.Type: GrantFiled: September 18, 2008Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park -
Publication number: 20100190315Abstract: There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer.Type: ApplicationFiled: November 5, 2009Publication date: July 29, 2010Inventors: Hack Seob SHIN, Kyoung Hwan Park
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Patent number: 7629245Abstract: A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripheral region. A contact region of the capping layer is etched. A spacer is formed on sidewalls of the capping layer. A contact region of the blocking oxide layer is etched by using the spacer as a mask. The spacer is removed while etching a contact region of the trap nitride layer. A contact region of the tunneling layer is etched.Type: GrantFiled: May 16, 2007Date of Patent: December 8, 2009Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Hwan Park
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Publication number: 20090296476Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.Type: ApplicationFiled: September 18, 2008Publication date: December 3, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Patent number: 7616496Abstract: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.Type: GrantFiled: June 29, 2007Date of Patent: November 10, 2009Assignee: Hynix Semiconductor Inc.Inventors: Eun Seok Choi, Se Jun Kim, Kyoung Hwan Park, Hyun Seung Yoo
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Publication number: 20080230830Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO