Patents by Inventor Kyoung-Hwan Yeo

Kyoung-Hwan Yeo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10824392
    Abstract: An electronic apparatus is provided. The electronic device includes a housing, a touch screen display disposed inside the housing and exposed through a first portion of the housing, a microphone disposed inside the housing and exposed through a second portion of the housing, a communication circuit disposed inside the housing, a processor disposed inside the housing and electrically connected to the touch screen display, the microphone, and the communication circuit, and a memory disposed in the housing and electrically connected with the processor.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Hwan Kim, Sun Key Lee, Kyung Tae Kim, Jae Yung Yeo, Kyoung Gu Woo, Jeong Hyeon Yun, Dong Sun Lim, Seong Min Je
  • Patent number: 10804264
    Abstract: An integrated circuit device includes a substrate from which a plurality of fin-type active regions protrude, the plurality of fin-type active regions extending in parallel to one another in a first direction, and a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction, wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a pair of gate structures from among the plurality of gate structures, and the plurality of fin-type active regions include a plurality of first fin-type regions and a plurality of second fin-type regions.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Il-ryong Kim, Ju-youn Kim, Jin-wook Kim, Kyoung-hwan Yeo, Yong-gi Jeong
  • Patent number: 10763156
    Abstract: An integrated circuit device includes a substrate having a first region and a second region, a first fin-isolation insulating portion in each of the first region and the second region and having a first width in a first direction, a pair of fin-type active regions spaced apart from each other in each of the first region and the second region with the first fin-isolation insulating portion therebetween, and extending in a straight line in the first direction, a pair of second fin-isolation insulating portions contacting, in each of the first region and the second region, two side walls of the first fin-isolation insulating portion, respectively, each of the two side walls facing the opposite sides in the first direction, and a plurality of gate structures extending in the second direction and comprising a plurality of dummy gate structures.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Il-ryong Kim, Ju-youn Kim, Jin-wook Kim, Kyoung-hwan Yeo, Yong-gi Jeong
  • Publication number: 20200251472
    Abstract: An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-seong LEE, Ju-youn KIM, Ji-hoon YOON, Il-ryong KIM, Kyoung-hwan YEO, Jae-yup CHUNG
  • Patent number: 10685960
    Abstract: An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-seong Lee, Ju-youn Kim, Ji-hoon Yoon, Il-ryong Kim, Kyoung-hwan Yeo, Jae-yup Chung
  • Patent number: 10672890
    Abstract: An integrated circuit device includes a substrate including a first device region and a second device region; a first fin separation insulating portion on the first device region; a pair of first fin-type active regions spaced from each other with the first fin separation insulating portion therebetween in the first device region and collinearly extending in a first horizontal direction; a second fin separation insulating portion extending in a second horizontal direction over the first device region and the second device region; and a pair of second fin-type active regions spaced from each other with the second fin separation insulating portion therebetween and collinearly extending in the first horizontal direction, wherein the first fin separation insulating portion and the second fin separation insulating portion vertically overlap each other.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-seong Lee, Il-ryong Kim, Kyoung-hwan Yeo, Jae-yup Chung
  • Patent number: 10566326
    Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae Young Kwak, Ki Byung Park, Kyoung Hwan Yeo, Seung Jae Lee, Kyung Yub Jeon, Seung Seok Ha, Sang Jin Hyun
  • Publication number: 20190385915
    Abstract: A semiconductor device includes a substrate including at least a first region, first active patterns and a first dummy pattern which vertically protrude from the first region, a device isolation layer filling a first trench, a second trench and a third trench of the substrate, and a gate electrode intersecting the first active patterns. The first trench defines the first active patterns on the first region, the second trench defines a first sidewall of the first region, and the third trench defines a second sidewall of the first region, which is opposite to the first sidewall. A sidewall of the first dummy pattern is aligned with the second sidewall of the first region, and a level of a top of the second sidewall of the first region is higher than a level of a top of the first sidewall of the first region.
    Type: Application
    Filed: January 16, 2019
    Publication date: December 19, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Youngmin PARK, Kyoung Hwan YEO, Jong Mil YOUN, Hwasung RHEE
  • Publication number: 20190326158
    Abstract: An integrated circuit device includes a substrate having a first region and a second region, a first fin-isolation insulating portion in each of the first region and the second region and having a first width in a first direction, a pair of fin-type active regions spaced apart from each other in each of the first region and the second region with the first fin-isolation insulating portion therebetween, and extending in a straight line in the first direction, a pair of second fin-isolation insulating portions contacting, in each of the first region and the second region, two side walls of the first fin-isolation insulating portion, respectively, each of the two side walls facing the opposite sides in the first direction, and a plurality of gate structures extending in the second direction and comprising a plurality of dummy gate structures.
    Type: Application
    Filed: October 19, 2018
    Publication date: October 24, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, II-ryong Kim, Ju-youn Kim, Jin-wook Kim, Kyoung-hwan Yeo, Yong-gi Jeong
  • Publication number: 20190319027
    Abstract: An integrated circuit device includes a substrate from which a plurality of fin-type active regions protrude, the plurality of fin-type active regions extending in parallel to one another in a first direction, and a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction, wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a pair of gate structures from among the plurality of gate structures, and the plurality of fin-type active regions include a plurality of first fin-type regions and a plurality of second fin-type regions.
    Type: Application
    Filed: October 25, 2018
    Publication date: October 17, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup CHUNG, II-ryong KIM, Ju-youn KIM, Jin-wook KIM, Kyoung-hwan YEO, Yong-gi JEONG
  • Patent number: 10446561
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Publication number: 20190312034
    Abstract: An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.
    Type: Application
    Filed: October 23, 2018
    Publication date: October 10, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-seong LEE, Ju-youn KIM, Ji-hoon YOON, II-ryong KIM, Kyoung-hwan YEO, Jae-yup CHUNG
  • Publication number: 20190312130
    Abstract: An integrated circuit device includes a substrate including a first device region and a second device region; a first fin separation insulating portion on the first device region; a pair of first fin-type active regions spaced from each other with the first fin separation insulating portion therebetween in the first device region and collinearly extending in a first horizontal direction; a second fin separation insulating portion extending in a second horizontal direction over the first device region and the second device region; and a pair of second fin-type active regions spaced from each other with the second fin separation insulating portion therebetween and collinearly extending in the first horizontal direction, wherein the first fin separation insulating portion and the second fin separation insulating portion vertically overlap each other.
    Type: Application
    Filed: October 22, 2018
    Publication date: October 10, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-seong Lee, Il-ryong Kim, Kyoung-hwan Yeo, Jae-yup Chung
  • Publication number: 20190257681
    Abstract: According to an exemplary embodiment, a microneedle probe device for measuring a sap flow rate of a plant includes: a substrate, of which at least a part is inserted into a plant, and a thickness and a width are microscales; a single metal wire provided on the substrate; a power source, which applies a current to the metal wire for a predetermined time and heats the metal wire; and a processor, which calculates a flow rate of sap through a movement of heat generated in the metal wire according to a flow of the sap within the plant.
    Type: Application
    Filed: June 14, 2017
    Publication date: August 22, 2019
    Inventors: Jung Hoon Lee, Sang Woong Baek, Eun Yong Jeon, Seung Yul Choi, Kyoung Sub Park, Joon Kook Kwon, Kyung Hwan Yeo, In Ho Yu, Jae Han Lee
  • Publication number: 20190155571
    Abstract: An electronic device is provided. The electronic device includes a housing, a touchscreen display exposed through a first portion of the housing, a microphone disposed at a second portion of the housing, a speaker disposed at a third portion of the housing, a memory disposed inside the housing, a processor disposed inside the housing, and electrically connected to the display, the microphone, the speaker, and the memory. The memory is configured to store a plurality of application programs, each of which includes a graphic user interface (GUI).
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: In Jong RHEE, Ji Min LEE, Sang Ki KANG, Han Jun KU, Sung Pa PARK, Jang Seok SEO, In Wook SONG, Won Ick AHN, Kyoung Gu WOO, Ji Soo YI, Chang Kyun JEON, Ho Jun JAYGARL, Il Hwan CHOI, Yoo Jin HONG, Ji Hyun KIM, Jae Yung YEO
  • Publication number: 20180374859
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Application
    Filed: August 29, 2018
    Publication date: December 27, 2018
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10096605
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10043873
    Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate electrode crossing the active pattern and a capping structure on the gate electrode. The capping structure includes first and second capping patterns that are sequentially stacked on the gate electrode. The second capping pattern completely covers a top surface of the first capping pattern, and a dielectric constant of the second capping pattern is greater than that of the first capping pattern.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Hwan Yeo, Seonguk Park, Seungjae Lee, Doyoung Choi, Sunhom Steve Paak, Tae Eung Yoon, Dongho Cha, Ruiyi Chen
  • Patent number: 9978746
    Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device may include a substrate including an active pattern, a separation structure crossing the active pattern and dividing the active pattern into first and second region. The separation structure may include a first insulating pattern that fills a recess region between the first and second regions. The first insulating pattern may have a concave top surface.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Hwan Yeo, KeunHee Bai, Seungseok Ha, Eunsil Park, Sunhom Steve Paak, Heonjong Shin, Dongho Cha
  • Patent number: 9947672
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: April 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon