Patents by Inventor Kyoung Ik Cho

Kyoung Ik Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10629744
    Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 21, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
  • Patent number: 10598558
    Abstract: Provided is a pressure sensing element including a first electrode, a pressure sensing unit on the first electrode, a second electrode disposed on the pressure sensing unit and having first and second points on a top surface thereof, a first elastic member on the second electrode, and a second elastic member on the first elastic electrode, wherein a thickness of the first elastic member decreases from the first point toward the second point, and a thickness of the second elastic member increases from the second point toward the first point.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: March 24, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seong Hyun Kim, Su Jae Lee, Kyoung Ik Cho, Chi-Sun Hwang
  • Publication number: 20180277684
    Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
  • Publication number: 20180246000
    Abstract: Provided is a pressure sensing element including a first electrode, a pressure sensing unit on the first electrode, a second electrode disposed on the pressure sensing unit and having first and second points on a top surface thereof, a first elastic member on the second electrode, and a second elastic member on the first elastic electrode, wherein a thickness of the first elastic member decreases from the first point toward the second point, and a thickness of the second elastic member increases from the second point toward the first point.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 30, 2018
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seong Hyun KIM, Su Jae LEE, Kyoung Ik CHO, Chi-Sun HWANG
  • Patent number: 10026844
    Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: July 17, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
  • Patent number: 10008155
    Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 26, 2018
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIV
    Inventors: Chunwon Byun, Jong-Heon Yang, Sung-Min Yoon, Kyoung Ik Cho, Chi-Sun Hwang
  • Patent number: 9952460
    Abstract: Provided is a display device. The display device includes a lower display element where a substrate, a first lower electrode, a liquid crystal part, and a second lower electrode are sequentially stacked, an upper display element stacked vertical to the lower display element, where a first upper electrode, a light emitting part, a second upper electrode, and a protective part are sequentially stacked, and a middle part configured to deliver a driving signal to the lower and upper display elements, between the lower and upper display elements.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 24, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong-Heon Yang, Jae Bon Koo, Byoung-Hwa Kwon, Gi Heon Kim, Yong Hae Kim, Hojun Ryu, Chan Woo Park, Chunwon Byun, Hyunkoo Lee, Jong Tae Lim, Kyoung Ik Cho, Seong-Mok Cho, Hye Yong Chu, Chi-Sun Hwang
  • Publication number: 20180026104
    Abstract: Provided are a p-type oxide semiconductor, a method of forming the p-type oxide semiconductor, and a transistor with the p-type oxide semiconductor. The p-type oxide semiconductor includes an alkali metal and a tin oxide.
    Type: Application
    Filed: June 13, 2017
    Publication date: January 25, 2018
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Haeng CHO, Sooji NAM, Chi-Sun HWANG, Su Jae LEE, Kyoung Ik CHO, Jae-Eun PI
  • Patent number: 9728149
    Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: August 8, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chunwon Byun, Jae-Eun Pi, Kyoung Ik Cho, Hye Yong Chu, Chi-Sun Hwang
  • Publication number: 20170186876
    Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
    Type: Application
    Filed: March 17, 2017
    Publication date: June 29, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
  • Patent number: 9634120
    Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 25, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
  • Publication number: 20170032741
    Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 2, 2017
    Inventors: Chunwon BYUN, Jong-Heon YANG, Sung-Min YOON, Kyoung Ik CHO, Chi-Sun HWANG
  • Publication number: 20160267827
    Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.
    Type: Application
    Filed: January 27, 2016
    Publication date: September 15, 2016
    Inventors: Chunwon BYUN, Jae-Eun PI, Kyoung Ik CHO, Hye Yong CHU, Chi-Sun HWANG
  • Publication number: 20160246116
    Abstract: Provided is a display device. The display device includes a lower display element where a substrate, a first lower electrode, a liquid crystal part, and a second lower electrode are sequentially stacked, an upper display element stacked vertical to the lower display element, where a first upper electrode, a light emitting part, a second upper electrode, and a protective part are sequentially stacked, and a middle part configured to deliver a driving signal to the lower and upper display elements, between the lower and upper display elements.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 25, 2016
    Inventors: Jong-Heon YANG, Jae Bon KOO, Byoung-Hwa KWON, Gi Heon KIM, Yong Hae KIM, Hojun RYU, Chan Woo PARK, Chunwon BYUN, Hyunkoo LEE, Jong Tae LIM, Kyoung Ik CHO, Seong-Mok CHO, Hye Yong CHU, Chi-Sun HWANG
  • Patent number: 9331126
    Abstract: Provided is a method for fabricating a flexible display device. The method includes attaching a shape memory alloy film memorizing a shape thereof as a curved shape at a shape memory temperature or lower to a flexible substrate at a temperature higher than the shape memory temperature, forming a display device on the flexible substrate, and returning the shape memory alloy to the curved shape to remove the shape memory alloy film from the flexible substrate.
    Type: Grant
    Filed: May 17, 2014
    Date of Patent: May 3, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Seok Lee, Kyoung Ik Cho, Bock Soon Na, Sang Chul Lim, Chan Woo Park, Soon-Won Jung, Jae Bon Koo, Hye Yong Chu
  • Publication number: 20150348800
    Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
    Type: Application
    Filed: January 30, 2015
    Publication date: December 3, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
  • Publication number: 20150349136
    Abstract: Methods for manufacturing semiconductor devices according to embodiments of the present invention may include providing a sacrificial substrate including a wiring region and a device region, sequentially forming a sacrificial layer and a buffer layer on the sacrificial substrate, forming a thin-film transistor on the buffer layer of the device region, forming a device protection element surrounding the thin-film transistor within the device region, forming a flexible substrate on the buffer layer, and exposing a surface of the buffer layer by separating the sacrificial substrate by removing the sacrificial layer. Since typical semiconductor process technologies may be directly used, the process compatibility may be improved, and semiconductor devices having high resolution and high performance may be manufactured.
    Type: Application
    Filed: January 30, 2015
    Publication date: December 3, 2015
    Inventors: Jae Bon KOO, Chan Woo PARK, Soon-Won JUNG, Bock Soon NA, Sang Chul LIM, Sang Seok LEE, Kyoung Ik CHO, Hye Yong CHU
  • Patent number: 9177821
    Abstract: Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: November 3, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soon-Won Jung, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Chul Lim, Sang Seok Lee, Kyoung Ik Cho, Hye Yong Chu
  • Patent number: 9153651
    Abstract: Provided are a thin film transistor and a method for manufacturing the same. The thin film transistor manufacturing method includes forming a gate electrode on a substrate, forming an active layer that is adjacent to the gate electrode and includes an oxide semiconductor, forming an oxygen providing layer on the active layer, forming a gate dielectric between the gate electrode and the active layer, forming source and drain electrodes coupled to the active layer, forming a planarizing layer covering the gate electrode and the gate dielectric, forming a hole exposing the active layer, and performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Chul Lim, Ji-Young Oh, Seongdeok Ahn, Kyoung Ik Cho, Sang Seok Lee, Jae Bon Koo
  • Publication number: 20150173186
    Abstract: Provided is a stretchable devices. The stretchable device includes a first stretchable substrate having a first wavy surface that wrinkles in a first direction; first wiring lines extending along the first wavy surface in the first direction; a second stretchable substrate having a second wavy surface that faces the first wavy surface and wrinkles in a second direction intersecting the first direction, wherein the second stretchable substrate is disposed on the first stretchable substrate; second wiring lines extending along the second wavy surface in the second direction; and interlayer insulating layers disposed on the intersections of the first wiring lines and the second wiring lines and disposed between the first wiring lines and the second wiring lines.
    Type: Application
    Filed: May 16, 2014
    Publication date: June 18, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Bock Soon NA, Soon-Won JUNG, Jae Bon KOO, Chan Woo PARK, Sang Chul LIM, Sang Seok LEE, Kyoung Ik CHO, Hye Yong CHU