Patents by Inventor Kyoung Ik Cho
Kyoung Ik Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10629744Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: GrantFiled: May 31, 2018Date of Patent: April 21, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
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Patent number: 10598558Abstract: Provided is a pressure sensing element including a first electrode, a pressure sensing unit on the first electrode, a second electrode disposed on the pressure sensing unit and having first and second points on a top surface thereof, a first elastic member on the second electrode, and a second elastic member on the first elastic electrode, wherein a thickness of the first elastic member decreases from the first point toward the second point, and a thickness of the second elastic member increases from the second point toward the first point.Type: GrantFiled: February 7, 2018Date of Patent: March 24, 2020Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong Hyun Kim, Su Jae Lee, Kyoung Ik Cho, Chi-Sun Hwang
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Publication number: 20180277684Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: ApplicationFiled: May 31, 2018Publication date: September 27, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
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Publication number: 20180246000Abstract: Provided is a pressure sensing element including a first electrode, a pressure sensing unit on the first electrode, a second electrode disposed on the pressure sensing unit and having first and second points on a top surface thereof, a first elastic member on the second electrode, and a second elastic member on the first elastic electrode, wherein a thickness of the first elastic member decreases from the first point toward the second point, and a thickness of the second elastic member increases from the second point toward the first point.Type: ApplicationFiled: February 7, 2018Publication date: August 30, 2018Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong Hyun KIM, Su Jae LEE, Kyoung Ik CHO, Chi-Sun HWANG
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Patent number: 10026844Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: GrantFiled: March 17, 2017Date of Patent: July 17, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
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Patent number: 10008155Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.Type: GrantFiled: July 27, 2016Date of Patent: June 26, 2018Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVInventors: Chunwon Byun, Jong-Heon Yang, Sung-Min Yoon, Kyoung Ik Cho, Chi-Sun Hwang
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Patent number: 9952460Abstract: Provided is a display device. The display device includes a lower display element where a substrate, a first lower electrode, a liquid crystal part, and a second lower electrode are sequentially stacked, an upper display element stacked vertical to the lower display element, where a first upper electrode, a light emitting part, a second upper electrode, and a protective part are sequentially stacked, and a middle part configured to deliver a driving signal to the lower and upper display elements, between the lower and upper display elements.Type: GrantFiled: January 29, 2016Date of Patent: April 24, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Heon Yang, Jae Bon Koo, Byoung-Hwa Kwon, Gi Heon Kim, Yong Hae Kim, Hojun Ryu, Chan Woo Park, Chunwon Byun, Hyunkoo Lee, Jong Tae Lim, Kyoung Ik Cho, Seong-Mok Cho, Hye Yong Chu, Chi-Sun Hwang
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Publication number: 20180026104Abstract: Provided are a p-type oxide semiconductor, a method of forming the p-type oxide semiconductor, and a transistor with the p-type oxide semiconductor. The p-type oxide semiconductor includes an alkali metal and a tin oxide.Type: ApplicationFiled: June 13, 2017Publication date: January 25, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Haeng CHO, Sooji NAM, Chi-Sun HWANG, Su Jae LEE, Kyoung Ik CHO, Jae-Eun PI
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Patent number: 9728149Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.Type: GrantFiled: January 27, 2016Date of Patent: August 8, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chunwon Byun, Jae-Eun Pi, Kyoung Ik Cho, Hye Yong Chu, Chi-Sun Hwang
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Publication number: 20170186876Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: ApplicationFiled: March 17, 2017Publication date: June 29, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
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Patent number: 9634120Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: GrantFiled: January 30, 2015Date of Patent: April 25, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
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Publication number: 20170032741Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.Type: ApplicationFiled: July 27, 2016Publication date: February 2, 2017Inventors: Chunwon BYUN, Jong-Heon YANG, Sung-Min YOON, Kyoung Ik CHO, Chi-Sun HWANG
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Publication number: 20160267827Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.Type: ApplicationFiled: January 27, 2016Publication date: September 15, 2016Inventors: Chunwon BYUN, Jae-Eun PI, Kyoung Ik CHO, Hye Yong CHU, Chi-Sun HWANG
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Publication number: 20160246116Abstract: Provided is a display device. The display device includes a lower display element where a substrate, a first lower electrode, a liquid crystal part, and a second lower electrode are sequentially stacked, an upper display element stacked vertical to the lower display element, where a first upper electrode, a light emitting part, a second upper electrode, and a protective part are sequentially stacked, and a middle part configured to deliver a driving signal to the lower and upper display elements, between the lower and upper display elements.Type: ApplicationFiled: January 29, 2016Publication date: August 25, 2016Inventors: Jong-Heon YANG, Jae Bon KOO, Byoung-Hwa KWON, Gi Heon KIM, Yong Hae KIM, Hojun RYU, Chan Woo PARK, Chunwon BYUN, Hyunkoo LEE, Jong Tae LIM, Kyoung Ik CHO, Seong-Mok CHO, Hye Yong CHU, Chi-Sun HWANG
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Patent number: 9331126Abstract: Provided is a method for fabricating a flexible display device. The method includes attaching a shape memory alloy film memorizing a shape thereof as a curved shape at a shape memory temperature or lower to a flexible substrate at a temperature higher than the shape memory temperature, forming a display device on the flexible substrate, and returning the shape memory alloy to the curved shape to remove the shape memory alloy film from the flexible substrate.Type: GrantFiled: May 17, 2014Date of Patent: May 3, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Seok Lee, Kyoung Ik Cho, Bock Soon Na, Sang Chul Lim, Chan Woo Park, Soon-Won Jung, Jae Bon Koo, Hye Yong Chu
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Publication number: 20150348800Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: ApplicationFiled: January 30, 2015Publication date: December 3, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
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Publication number: 20150349136Abstract: Methods for manufacturing semiconductor devices according to embodiments of the present invention may include providing a sacrificial substrate including a wiring region and a device region, sequentially forming a sacrificial layer and a buffer layer on the sacrificial substrate, forming a thin-film transistor on the buffer layer of the device region, forming a device protection element surrounding the thin-film transistor within the device region, forming a flexible substrate on the buffer layer, and exposing a surface of the buffer layer by separating the sacrificial substrate by removing the sacrificial layer. Since typical semiconductor process technologies may be directly used, the process compatibility may be improved, and semiconductor devices having high resolution and high performance may be manufactured.Type: ApplicationFiled: January 30, 2015Publication date: December 3, 2015Inventors: Jae Bon KOO, Chan Woo PARK, Soon-Won JUNG, Bock Soon NA, Sang Chul LIM, Sang Seok LEE, Kyoung Ik CHO, Hye Yong CHU
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Patent number: 9177821Abstract: Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.Type: GrantFiled: April 22, 2014Date of Patent: November 3, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Soon-Won Jung, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Chul Lim, Sang Seok Lee, Kyoung Ik Cho, Hye Yong Chu
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Patent number: 9153651Abstract: Provided are a thin film transistor and a method for manufacturing the same. The thin film transistor manufacturing method includes forming a gate electrode on a substrate, forming an active layer that is adjacent to the gate electrode and includes an oxide semiconductor, forming an oxygen providing layer on the active layer, forming a gate dielectric between the gate electrode and the active layer, forming source and drain electrodes coupled to the active layer, forming a planarizing layer covering the gate electrode and the gate dielectric, forming a hole exposing the active layer, and performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen.Type: GrantFiled: February 1, 2013Date of Patent: October 6, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Chul Lim, Ji-Young Oh, Seongdeok Ahn, Kyoung Ik Cho, Sang Seok Lee, Jae Bon Koo
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Publication number: 20150173186Abstract: Provided is a stretchable devices. The stretchable device includes a first stretchable substrate having a first wavy surface that wrinkles in a first direction; first wiring lines extending along the first wavy surface in the first direction; a second stretchable substrate having a second wavy surface that faces the first wavy surface and wrinkles in a second direction intersecting the first direction, wherein the second stretchable substrate is disposed on the first stretchable substrate; second wiring lines extending along the second wavy surface in the second direction; and interlayer insulating layers disposed on the intersections of the first wiring lines and the second wiring lines and disposed between the first wiring lines and the second wiring lines.Type: ApplicationFiled: May 16, 2014Publication date: June 18, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Bock Soon NA, Soon-Won JUNG, Jae Bon KOO, Chan Woo PARK, Sang Chul LIM, Sang Seok LEE, Kyoung Ik CHO, Hye Yong CHU