Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: Disclosed is a semiconductor test system which includes a plurality of test stations, a plurality of test pattern generators corresponding to the test stations and a plurality of comparators corresponding to the test stations. Semiconductor devices under test are mounted on each of the plurality of test stations. Each of the test pattern generators generates test patterns and expected data in response to a test command from a host. Each of the comparators compares data from semiconductor devices on a corresponding test station with the expected data. In particular, semiconductor devices on at least one of the test stations may be of different type from those on each of remaining test stations. The semiconductor test system is capable of testing semiconductor devices on the test stations in parallel at the same. This test scheme allows for decrease in the time and cost that are needed to test different types of semiconductor devices.