Abstract: A liquid crystal display includes a first substrate, a gate line disposed on an upper portion of the first substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode and defines a contact hole which exposes a part of the drain electrode, a common electrode provided at an upper portion of the passivation layer and having a planar structure, a pixel electrode electrically connected to the drain electrode through the contact hole and including a plurality of pixel branch electrodes, and a second substrate corresponding to the first substrate, where an opening is defined in the common electrode at a position which corresponds to a middle region of the plurality of pixel branch electrodes.

Abstract: An image processing part includes an edge enhancing part, an artifact detecting part and a compensating part. The edge enhancing part emphasizes an edge portion of an object in input image data. The artifact detecting part detects a corner outlier artifact at an area adjacent to the edge portion of the object. The compensating part compensates the corner outlier artifact. Accordingly, the edge portion of the object may be enhanced and the corner outlier artifact is decreased so that the display quality may be improved.

Abstract: A stage includes first, second, and third outputs and first and second signal processors. The first output supplies a scan signal to a first output terminal based on signals to first and second input terminals and the voltage of a first node. The second output is connected to a first power source and supplies an emission control signal to a second output terminal based on signals to the first input terminal, the first output terminal, and a third input terminal. The third output is connected to the first power source and supplies an inverted emission control signal to a third output terminal based on signals to the first input terminal and second output terminal. The first signal processor controls the first node voltage based on a signal to a fourth input terminal. The second signal processor controls the first node voltage based on the signal to the second input terminal.

Abstract: A display panel driver includes a plurality of stages. An N-th stage of the plurality of stages is configured to output a scan signal and an emission signal synchronized with each other based on a first power voltage, a second power voltage, and at least one clock signal. N is a natural number.

Abstract: A display device and method of manufacture includes a substrate; a transistor disposed on the substrate to include a gate electrode, a semiconductor layer, a source electrode, a drain electrode, and a gate insulating layer disposed between the gate electrode and the semiconductor layer. A capacitor disposed on the substrate includes a first electrode, a second electrode, and a dielectric layer is disposed between the first electrode and the second electrode. The dielectric layer has a thickness that is thinner than a thickness of the gate insulating layer.

Abstract: An emission control driver includes a plurality of stages configured to output a plurality of emission control signals, respectively. Each stage includes an input circuit for receiving a previous emission control signal from one of previous stages or a vertical start signal, and configured to control a voltage of a first node and a voltage of a second node in response to a first clock signal; a stabilizing circuit for stabilizing the voltage of the first node in response to the voltage of the second node and a second clock signal; a voltage adjusting circuit connected between the second node and a third node, configured for boosting the voltage of the second node, and controlling the boosted voltage of the second node; and an output circuit configured to control an emission control signal in response to the voltage of the first node and a voltage of the third node.

Abstract: A gate driver includes a plurality of stages outputting a plurality of gate output signals, respectively. Each stage includes a first input circuit applying an input signal to a first node in response to a first clock signal, a second input circuit applying the first clock signal to a second node in response to a voltage of the first node, a first output circuit controlling a gate output signal to a first logic level in response to the voltage of the first node, a second output circuit controlling the gate output signal to a second logic level in response to a voltage of the second node, and a leakage current blocking circuit applying a first power voltage corresponding to the first logic level to the first input circuit in response to the voltage of the first node.

Abstract: A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.

Abstract: An image processing part includes an edge enhancing part, an artifact detecting part and a compensating part. The edge enhancing part emphasizes an edge portion of an object in input image data. The artifact detecting part detects a corner outlier artifact at an area adjacent to the edge portion of the object. The compensating part compensates the corner outlier artifact. Accordingly, the edge portion of the object may be enhanced and the corner outlier artifact is decreased so that the display quality may be improved.

Abstract: A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.

Abstract: In a liquid crystal display, a pretilt value provided by an upper alignment layer or a lower alignment layer is gradually changed in one domain, such that liquid crystal molecules have various arrangements in which azimuth angles of aligned liquid crystal molecules are gradually changed.

Abstract: Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.

Abstract: In a scan driver including a plurality of stages configured to supply scan signals to scan lines, the scan driver includes: an i?1th stage configured to supply an i?1th scan signal to an i?1th scan line while controlling a node Qi?1 (i is a natural number) in response to a first clock signal, a third clock signal, and a control voltage; an ith stage configured to supply an ith scan signal to an ith scan line while controlling a node Qi in response to a second clock signal, a fourth clock signal, and the control voltage; and a controller connected to the i?1th stage and the ith stage, and configured to supply the control voltage.

Abstract: A display device includes a substrate, a thin film transistor, a storage electrode, a pixel electrode, and a common electrode. The thin film transistor is disposed on the substrate and includes a drain electrode and a semiconductor layer. The storage electrode is disposed at a same layer as the semiconductor layer. The pixel electrode is disposed on the substrate and is electrically connected to the drain electrode. The common electrode is disposed on the substrate.

Abstract: A display panel includes a gate line, first and second data lines, first and second gate control lines, and first and second pixels. The first pixel includes a double-gate switching element including a gate electrode connected to the gate line, a source electrode connected to the first data line, and another gate electrode connected to the first gate control line. The second pixel includes a double-gate switching element including a gate electrode connected to the gate line, a source electrode connected to the second data line, and a gate electrode connected to the second gate control line. A data voltage having a first polarity is applied to the first data line, another data voltage having a second polarity is applied to the second data line, and first and second gate control voltages are respectively applied to the first and second gate control lines.

Abstract: A gate driving circuit includes driving stages to provide gate signals to gate lines of a display panel, a k-th driving stage (where k is a natural number greater than 2) of the driving stages including an output unit to output a k-th gate signal to a k-th gate line and a k-th carry signal to a k-th carry terminal in response to a voltage of a first node, a control unit to control a potential of the first node, a pull-down unit to pull down the k-th gate line and the k-th carry terminal to a ground voltage in response to a (k+1)-th carry signal, and a reset unit to reset the voltage of the first node to the ground voltage in response to the reset signal. The reset unit receives one of the k-th gate signal and the k-th carry signal as a feedback signal.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A gate driving circuit including a plurality of stage circuits to output a plurality of gate signals, a N-th stage circuit of the plurality of stage circuits includes: an output pull-up part including a control electrode connected to a first node, the first node being configured to have a potential increase in response to a (N?1)-th control signal received from a previous stage circuit of the N-th stage circuit, the output pull-up part to receive a clock signal to output a gate signal of the N-th stage circuit; a control node pull-up part to control the potential of the first node by using the (N?1)-th control signal; and a control node pull-down part to discharge the first node to a second low voltage according to a (N+1)-th control signal, wherein the output pull-up part is to discharge the gate signal of the N-th stage circuit in a (N+2)-th stage circuit.