Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract: A panel assembly for a display device and a display device having the panel assembly are provided. The panel assembly for a display device includes a display region including a plurality of pixels and most of display signal lines connected to the pixels, a plurality of repair lines disposed in a shape of a ring in a peripheral region outside of the display region, and first to third auxiliary repair lines disposed in the peripheral region in parallel to data lines. An additional auxiliary repair line is provided at a right side of each of the data driving IC regions. By doing so, occurrence of disconnection and success in repairing the disconnected data lines of a display penal which is mounted in a COG scheme is tested by using a TCP type of test unit, so that it is possible to greatly reduce production costs involved in the COG type test unit.

Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract: A mother display panel that is capable of being divided into multiple display panels precisely and efficiently is presented. The mother display panel includes a plurality of cutting mark groups which is arranged in a matrix pattern to serve as a position reference for corners of the plurality of display panels. The respective cutting mark groups include unit cutting marks that are spaced from each other.

Abstract: A liquid crystal display apparatus includes a first substrate on which a pixel area is defined, a second substrate facing the first substrate, and liquid crystals interposed between the first and second substrates. The pixel area is divided into a plurality of domains according to the alignment direction of the liquid crystals. The domains compensate for optical characteristics, thereby widening the viewing angle of the liquid crystal display apparatus. The liquid crystals include smectic liquid crystals that form a layered structure in a specific direction. When the liquid crystal display apparatus is driven, the smectic liquid crystals rapidly respond to the electric field, thereby improving the operational speed of the liquid crystal apparatus.

Abstract: A panel assembly for a display device and a display device having the panel assembly are provided. The panel assembly for a display device includes a display region including a plurality of pixels and most of display signal lines connected to the pixels, a plurality of repair lines disposed in a shape of a ring in a peripheral region outside of the display region, and first to third auxiliary repair lines disposed in the peripheral region in parallel to data lines. An additional auxiliary repair line is provided at a right side of each of the data driving IC regions. By doing so, occurrence of disconnection and success in repairing the disconnected data lines of a display penal which is mounted in a COG scheme is tested by using a TCP type of test unit, so that it is possible to greatly reduce production costs involved in the COG type test unit.