Abstract: Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

Abstract: A tile-based rendering apparatus and method is provided. Vertex data sorted based on a tile unit may be stored in a scene buffer and be rendered. Among the stored vertex data, vertex data used several times for rendering may be temporarily stored in a memory or a cache. Vertex data having a probability of being read several times from the scene buffer may be temporarily stored in another memory.

Abstract: A system and method of rendering three-dimensional (3D) graphics. The system for rendering 3D graphics may include a plurality of cores including a scratch pad memory, a first memory to perform a control flow, a second memory for loop acceleration, and a shared memory to interpolate with the plurality of cores.

Abstract: A method and apparatus for processing a vertex may fetch pieces of position information of vertexes, may extract pieces of target position information from the fetched pieces of position information, may perform tile binning on the pieces of target position information, may fetch pieces of attribute information having same indexes as the pieces of target position information, and may shade the fetched pieces of attribute information.

Abstract: An apparatus for and method of processing a vertex in relation to 3 dimensional (3D) graphics pipeline are provided. According to the method, while a processor processes vertex data in units of batches, vertex data corresponding to a batch to be processed next is extracted and temporarily stored in a buffer independently of the processor. If the processor finishes processing of the current batch, the batch stored in the buffer is output so that the processor can immediately process the batch.

Abstract: A method to discard pixels early includes a first early depth test maintaining a depth value on a pixel to be discarded by a discard instruction, and a second early depth test updating the depth value on a pixel not to be discarded by the discard instruction. Because of the first and second early depth tests, a number of pixels to be processed by a pixel shading process may be reduced.

Abstract: A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Abstract: A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.

Abstract: Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.

Abstract: A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

Abstract: A method and apparatus for processing a vertex may fetch pieces of position information of vertexes, may extract pieces of target position information from the fetched pieces of position information, may perform tile binning on the pieces of target position information, may fetch pieces of attribute information having same indexes as the pieces of target position information, and may shade the fetched pieces of attribute information.

Abstract: Disclosed are an apparatus and a method for back-face culling using coherence between chronologically adjacent frames. The apparatus and the method determine whether face properties of polygons are changed based on a matrix reflecting three-dimensional motion of a frame. When the face properties are not changed, face properties of the polygons used in a process of a previous frame are reused to cull back-face polygons.

Abstract: A method to discard pixels early includes a first early depth test maintaining a depth value on a pixel to be discarded by a discard instruction, and a second early depth test updating the depth value on a pixel not to be discarded by the discard instruction. Because of the first and second early depth tests, a number of pixels to be processed by a pixel shading process may be reduced.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: An image interpolation method interpolating image information of a point in a space constructed by a plurality of planes. According to the method, a reliable interpolated value can be rapidly obtained by searching for the nearest plane to the point, obtaining information about a plane facing the nearest plane using image information of one or more vertices of the plane facing the nearest plane, and interpolating the image information of the point using the image information of the one or more vertices of the nearest plane and the obtained information about the plane facing the nearest plane.

Abstract: A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

Abstract: A tile-based rendering apparatus and method is provided. Vertex data sorted based on a tile unit may be stored in a scene buffer and be rendered. Among the stored vertex data, vertex data used several times for rendering may be temporarily stored in a memory or a cache. Vertex data having a probability of being read several times from the scene buffer may be temporarily stored in another memory.

Abstract: Provided is a method for converting a first image signal expressed in a first color space into a second image signal expressed in a second color space on a subword parallelism basis.

Abstract: Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

Abstract: A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.