Abstract: The present invention relates to a compound capable of lowering the flammability of a non-aqueous electrolyte when included in the non-aqueous electrolyte and improving the life properties of a battery by forming an electrode-electrolyte interface which is stable at high temperatures and low in resistance, and relates to a compound represented by Formula I descried herein, a non-aqueous electrolyte solution and a lithium secondary battery both including the compound, n, m, Ak, and X are described herein.

Abstract: An embodiment sulfur dioxide-based inorganic electrolyte is provided in which the sulfur dioxide-based inorganic electrolyte is represented by a chemical formula M·(A1·Cl(4-x)Fx)z·ySO2. In this formula, M is a first element selected from the group consisting of Li, Na, K, Ca, and Mg, A1 is a second element selected from the group consisting of Al, Fe, Ga, and Cu, x satisfies a first equation 0?x?4, y satisfies a second equation 0?y?6, and z satisfies a third equation 1?z?2.

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer. A modified access region is provided at an upper surface of the barrier layer opposite the channel layer. The modified access region includes a material having a lower surface barrier height than the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between source contact and the drain contact.

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

Abstract: A transistor includes a first passivation layer on a semiconductor layer of the transistor between a source contact and a drain contact. The first passivation layer includes a portion having a topological change. The transistor further includes a discontinuous barrier layer on the portion of the first passivation layer having the topological change. The discontinuous barrier layer is configured to reduce ingress of moisture in the portion of the first passivation layer.

Abstract: A device including a substrate, a passivation layer, a source, a gate, a drain, and the gate including at least one step portion. Where the at least one step portion is arranged within the passivation layer, the at least one step portion includes at least one first surface and at least one second surface, where the at least one first surface is connected to the at least one second surface, where the gate includes a third surface, and where the at least one step portion is connected to the third surface. A process is also disclosed.

Abstract: A transistor device includes a substrate, a gate contact pad on the substrate, and a transistor die on the substrate adjacent the gate contact pad. The transistor die includes an active region and a gate bond pad adjacent the active region, and the gate bond pad has a side edge adjacent the active region that extends in a first direction. The transistor device includes a bonding wire bonded to the gate contact pad at a first end of the bonding wire and to the gate bond pad at a second end of the bonding wire. The bonding wire extends in a second direction that is oblique to the first direction such that the bonding wire forms an angle relative to the first direction that is less than 90 degrees.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes first and second sublayers of first and second oxide materials, respectively, where the first oxide material is different than the second oxide material. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer. A modified access region is provided at an upper surface of the barrier layer opposite the channel layer. The modified access region includes a material having a lower surface barrier height than the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between source contact and the drain contact.

Abstract: A transistor device ac includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer, a source contact and a drain contact on the barrier layer, and a gate contact on the barrier layer between source contact and the drain contact. The device further includes a plurality of selective modified access regions at an upper surface of the barrier layer opposite the channel layer. The selective modified access regions include a material having a lower surface barrier height than the barrier layer, and the plurality of selective modified access regions are spaced apart on the barrier layer along a length of the gate contact.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: A process of forming a device with a pad structure having environmental protection includes providing a semiconductor body portion, arranging a pad on the semiconductor body portion, providing at least one environment encapsulation portion at least partially on the pad, arranging a supplemental pad on the pad, and arranging the supplemental pad to include side surfaces that extend vertically above the at least one environment encapsulation portion. A device having a pad structure having environmental protection is also disclosed.

Abstract: A device including a substrate, a passivation layer, a source, a gate, a drain, and the gate including at least one step portion. Where the at least one step portion is arranged within the passivation layer, the at least one step portion includes at least one first surface and at least one second surface, where the at least one first surface is connected to the at least one second surface, where the gate includes a third surface, and where the at least one step portion is connected to the third surface. A process is also disclosed.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.