Patents by Inventor Kyoung Lim SUK
Kyoung Lim SUK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10964643Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.Type: GrantFiled: November 26, 2019Date of Patent: March 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Lim Suk, Seokhyun Lee
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Publication number: 20210074754Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Inventors: JAEGWON JANG, SEOKHYUN LEE, KYOUNG LIM SUK
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Patent number: 10930625Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.Type: GrantFiled: June 4, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Lim Suk, Seokhyun Lee
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Patent number: 10879187Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.Type: GrantFiled: June 12, 2018Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Lim Suk, Seung-Kwan Ryu, Seokhyun Lee
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Patent number: 10879292Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.Type: GrantFiled: March 26, 2019Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jaegwon Jang, Seokhyun Lee, Kyoung Lim Suk
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Publication number: 20200328175Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the secondType: ApplicationFiled: June 28, 2020Publication date: October 15, 2020Inventors: Youn Ji Min, Seokhyun Lee, Jongyoun Kim, Kyoung Lim Suk, SeokWon Lee
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Patent number: 10741518Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the secondType: GrantFiled: November 27, 2019Date of Patent: August 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youn Ji Min, Seokhyun Lee, Jongyoun Kim, Kyoung Lim Suk, SeokWon Lee
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Publication number: 20200219834Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn KIM, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
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Patent number: 10622320Abstract: A semiconductor package may include a semiconductor chip; a molding portion configured to surround at least a side surface of the semiconductor chip; a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip; and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer.Type: GrantFiled: January 12, 2018Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn Kim, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
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Publication number: 20200111681Abstract: A method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer, and forming an upper re-distribution layer on the semiconductor chip and the stack.Type: ApplicationFiled: May 17, 2019Publication date: April 9, 2020Inventor: KYOUNG LIM SUK
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Publication number: 20200111747Abstract: A method of fabricating a semiconductor package may include forming a lower redistribution layer, forming a stack on a portion of the lower redistribution layer, and stacking a semiconductor chip on a top surface of the lower redistribution layer. The forming of the stack may include coating a photo imagable dielectric material to form a first insulating layer on the top surface of the lower redistribution layer, forming a first via to penetrate the first insulating layer, coating a photo imagable dielectric material to form a second insulating layer on a top surface of the first insulating layer, and forming a second via to penetrate the second insulating layer.Type: ApplicationFiled: May 14, 2019Publication date: April 9, 2020Inventor: Kyoung Lim SUK
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Publication number: 20200098716Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the secondType: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: Youn Ji MIN, Seokhyun LEE, Jongyoun KIM, Kyoung Lim SUK, SeokWon LEE
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Publication number: 20200098694Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Inventors: Kyoung Lim SUK, SEOKHYUN LEE
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Publication number: 20200091215Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.Type: ApplicationFiled: March 26, 2019Publication date: March 19, 2020Inventors: JAEGWON JANG, SEOKHYUN LEE, KYOUNG LIM SUK
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Publication number: 20200083201Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.Type: ApplicationFiled: June 4, 2019Publication date: March 12, 2020Inventors: KYOUNG LIM SUK, SEOKHYUN LEE
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Patent number: 10546829Abstract: A method of fabricating a semiconductor package including forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.Type: GrantFiled: January 10, 2018Date of Patent: January 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youn Ji Min, Seokhyun Lee, Jongyoun Kim, Kyoung Lim Suk, SeokWon Lee
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Patent number: 10522471Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.Type: GrantFiled: June 18, 2018Date of Patent: December 31, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Lim Suk, Seokhyun Lee
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Publication number: 20190051607Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.Type: ApplicationFiled: June 18, 2018Publication date: February 14, 2019Inventors: Kyoung Lim SUK, SEOKHYUN LEE
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Publication number: 20190035756Abstract: A method of fabricating a semiconductor package including, forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.Type: ApplicationFiled: January 10, 2018Publication date: January 31, 2019Inventors: YOUN JI MIN, Seokhyun LEE, Jongyoun KIM, Kyoung Lim SUK, SeokWon LEE
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Publication number: 20190027451Abstract: A semiconductor package may include a semiconductor chip; a molding portion configured to surround at least a side surface of the semiconductor chip; a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip; and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer.Type: ApplicationFiled: January 12, 2018Publication date: January 24, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn KIM, Seok-hyun LEE, Youn-ji MIN, Kyoung-lim SUK, Seok-won LEE