Patents by Inventor Kyoung-mok Son

Kyoung-mok Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9496016
    Abstract: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Jae Lee, Kyoung-Mok Son, Sang-Gi Ko, Si-Woo Kim
  • Publication number: 20140198560
    Abstract: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.
    Type: Application
    Filed: November 19, 2013
    Publication date: July 17, 2014
    Inventors: Choong-Jae LEE, Kyoung-Mok SON, Sang-Gi KO, Si-Woo KIM
  • Patent number: 7808468
    Abstract: A source driver for controlling a slew rate of a liquid crystal display (LCD) and a method for controlling the slew rate is provided. The source driver includes a plurality of output buffers for driving data lines, and a bias circuit for varying a bias voltage inputted to the output buffers to control a slew rate of the output buffers.
    Type: Grant
    Filed: June 3, 2006
    Date of Patent: October 5, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Mok Son, Soo-Cheol Lee
  • Patent number: 7791142
    Abstract: Provided is an electrostatic discharge (ESD) protection diode including: a well formed of a first conductivity in a semiconductor substrate; an active region that is formed of a second conductivity in the well and includes a plurality of first active lines extending in a first direction; a sub-region of the first conductivity including a plurality of first sub-lines extending in the first direction, the first sub lines being formed in the well, arranged to surround an outer region of the first active lines, and arranged in alternation with the first active lines; a device isolation region separating the active regions and the sub-regions; a plurality of active contacts arranged in a row in the active regions; and a plurality of sub-contacts arranged in a row in the sub-region.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-shik Kim, Kyoung-mok Son
  • Publication number: 20090273869
    Abstract: Provided is an electrostatic discharge (ESD) protection diode including: a well formed of a first conductivity in a semiconductor substrate; an active region that is formed of a second conductivity in the well and includes a plurality of first active lines extending in a first direction; a sub-region of the first conductivity including a plurality of first sub-lines extending in the first direction, the first sub lines being formed in the well, arranged to surround an outer region of the first active lines, and arranged in alternation with the first active lines; a device isolation region separating the active regions and the sub-regions; a plurality of active contacts arranged in a row in the active regions; and a plurality of sub-contacts arranged in a row in the sub-region.
    Type: Application
    Filed: November 6, 2008
    Publication date: November 5, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-shik Kim, Kyoung-mok Son
  • Publication number: 20070008009
    Abstract: A source driver for controlling a slew rate of a liquid crystal display (LCD) and a method for controlling the slew rate is provided. The source driver includes a plurality of output buffers for driving data lines, and a bias circuit for varying a bias voltage inputted to the output buffers to control a slew rate of the output buffers.
    Type: Application
    Filed: June 3, 2006
    Publication date: January 11, 2007
    Inventors: Kyoung-Mok Son, Soo-Cheol Lee
  • Patent number: 6552438
    Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: April 22, 2003
    Assignee: Samsung Electronics Co.
    Inventors: Soo-cheol Lee, Jong-hyon Ahn, Kyoung-mok Son, Heon-jong Shin, Hyae-ryoung Lee, Young-pill Kim, Moo-jin Jung, Son-jong Wang, Jae-Cheol Yoo
  • Publication number: 20010000928
    Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.
    Type: Application
    Filed: December 21, 2000
    Publication date: May 10, 2001
    Inventors: Soo-Cheol Lee, Jong-Hyon Ahn, Kyoung-Mok Son, Heon-Jong Shin, Hyae-Ryoung Lee, Young-Pill Kim, Moo-Jin Jung, Son-Jong Wang, Jae-Cheol Yoo