Patents by Inventor Kyoung Rouh

Kyoung Rouh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070120182
    Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.
    Type: Application
    Filed: June 9, 2006
    Publication date: May 31, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyoung Rouh, Seung Jin, Min Lee, Yong Jung
  • Publication number: 20070065999
    Abstract: A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.
    Type: Application
    Filed: June 9, 2006
    Publication date: March 22, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Min Lee, Kyoung Rouh, Seung Jin
  • Publication number: 20070004151
    Abstract: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.
    Type: Application
    Filed: November 29, 2005
    Publication date: January 4, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kyoung Rouh, Seung Jin, Min Lee
  • Publication number: 20070004159
    Abstract: Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation for formation of source/drain regions, on the entire surface of the semiconductor substrate having the gate stack formed thereon. In accordance with the present invention, since ion implantation is carried out after formation of the gate stack involving a thermal process, there are no changes in concentrations of implanted dopants due to heat treatment upon formation of the gate stack.
    Type: Application
    Filed: November 10, 2005
    Publication date: January 4, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung Jin, Min Lee, Kyoung Rouh
  • Publication number: 20060264013
    Abstract: An ion implantation method for manufacturing a semiconductor device in accordance with present invention is combined ion implantation of vertical ion implantation and tilted ion implantation. In accordance with the above-mentioned ion implantation method, a first dose of impurity ions, as a part of total dose of the impurity ions to be implanted, is first implanted by vertical ion implantation. Then, a remaining dose of impurity ions, except for the first dose from the total dose, is implanted by tilted ion implantation. Herein, tilted ion implantation may be subdivided into a plurality of tilted ion implantation.
    Type: Application
    Filed: December 14, 2005
    Publication date: November 23, 2006
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kyoung Rouh, Seung Jin, Sun Hwang
  • Publication number: 20060252217
    Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.
    Type: Application
    Filed: December 16, 2005
    Publication date: November 9, 2006
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kyoung Rouh, Seung Jin, Min Lee
  • Publication number: 20060211226
    Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.
    Type: Application
    Filed: August 4, 2005
    Publication date: September 21, 2006
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyoung Rouh, Yong Sohn, Min Lee
  • Publication number: 20060141690
    Abstract: Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped layer for a gate electrode; implanting mixed dopant ions consisting of at least two dopant ions containing 11B ions into the undoped layer, utilizing an ion-implantation mask; and heat-treating the mixed dopant ion-implanted layer.
    Type: Application
    Filed: August 11, 2005
    Publication date: June 29, 2006
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung Jin, Min Lee, Kyoung Rouh
  • Publication number: 20050136628
    Abstract: Disclosed are a method for implanting ions in a semiconductor process and a method for fabricating semiconductor devices using the same. The method for implanting ions comprises steps of: providing a semiconductor substrate; and implanting BF impurities or mixed BF2 and B11, impurities into the semiconductor substrate. The mixed BF2 and B11 impurities may be sequentially implanted, in the order of BF2 first and B11 second or in the order of B11 first and BF2 second, into the semiconductor substrate. If the ion implantation as described above is applied to a process for fabricating semiconductor devices, it is expected that refresh and cell current properties of semiconductor devices can be enhanced.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 23, 2005
    Inventors: Seung Jin, Bong Kim, Kyoung Rouh