Abstract: A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

Abstract: A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

Abstract: Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract: A motion vector extraction method includes: deciding on a search start position in an original video and performing a spiral motion search; and determining whether or not to perform a search in a sub-sampling video, during P picture search.

Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.

Abstract: An apparatus for distributing the bus traffic of the multiple camera inputs of an automotive system on chip (SoC) and an automotive SoC using the apparatus are disclosed. The plurality of camera data caches stores data from the plurality of cameras in corresponding internal buffers, measures the data storage status of the buffers, and transmits the data to memory. The bus monitor analyzes a bus signal, and then outputs a signal capable of allowing the plurality of camera data caches to transmit the data via the bus based on the results of the analysis. The master arbiter determines the priorities of use of the bus of the camera data caches, and provides the right to use the bus to the plurality of camera data caches based on the priorities of use of the bus.

Abstract: Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a node having a distributed memory and an auxiliary memory storing a sharer history table. The network load reducing method includes recording the history of a sharer node in the sharer history table of the auxiliary memory, requesting share data with reference to the sharer history table of the auxiliary memory, and deleting share data stored in the distributed memory and updating the sharer history table of the auxiliary memory.

Abstract: Provided is a method for partitioning a block in inter prediction including selecting one standard reference frame from at least one reference frame which is a comparison target in inter prediction, searching whether or not a higher-level macroblock of a current frame is partitioned based on the selected standard reference frame, determining a partition size of the higher-level macroblock of the current frame, searching whether or not the higher-level macroblock in which the partition size is determined is partitioned by comparing with any certain reference frame other than the standard reference frame, and stopping a block size search on the higher-level macroblock of the current frame if a partition size of the higher-level macroblock of the current frame determined by comparing with the standard reference frame and a partition size of the higher-level macroblock of the current frame determined by comparing with the certain reference frame are different from each other.

Abstract: A video encoding apparatus includes: a video preprocessor configured to receive video data; a video encoder configured to encode an output signal of the video preprocessor; a host controller configured to control operations of the video preprocessor and the video encoder; and an operating mode controlling circuit configured to output an encoding control signal to the video encoder to change a preprocessing operation once receiving a control parameter and an operation command from the host controller during the operation of the video encoder.

Abstract: A motion vector extraction method includes: deciding on a search start position in an original video and performing a spiral motion search; and determining whether or not to perform a search in a sub-sampling video, during P picture search.

Abstract: Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a node having a distributed memory and an auxiliary memory storing a sharer history table. The network load reducing method includes recording the history of a sharer node in the sharer history table of the auxiliary memory, requesting share data with reference to the sharer history table of the auxiliary memory, and deleting share data stored in the distributed memory and updating the sharer history table of the auxiliary memory.

Abstract: A video processing system includes a frame memory, an input video buffer, a macroblock buffer, a first search window buffer, a second search window buffer, a deblocked macroblock buffer, and a frame memory controller. The frame memory stores frame data. The input video buffer stores input data and transfers the input data to the frame memory. The macroblock buffer stores a plurality of macroblocks. The first search window buffer stores a search region of a reference frame for coarse motion estimation. The second search window buffer stores a search region of a reference frame for fine motion estimation. The deblocked macroblock buffer stores the performance results of a deblocking filter. The frame memory controller performs write/read operations on the input video buffer, the macroblock buffer, the first search window buffer, the second search window buffer, the deblocked macroblock buffer and the frame memory.

Abstract: Provided is a method for partitioning a block in inter prediction including selecting one standard reference frame from at least one reference frame which is a comparison target in inter prediction, searching whether or not a higher-level macroblock of a current frame is partitioned based on the selected standard reference frame, determining a partition size of the higher-level macroblock of the current frame, searching whether or not the higher-level macroblock in which the partition size is determined is partitioned by comparing with any certain reference frame other than the standard reference frame, and stopping a block size search on the higher-level macroblock of the current frame if a partition size of the higher-level macroblock of the current frame determined by comparing with the standard reference frame and a partition size of the higher-level macroblock of the current frame determined by comparing with the certain reference frame are different from each other.

Abstract: A method for managing a frame memory includes: determining a frame memory structure with reference to memory configuration information and image processing information; configuring a frame memory such that a plurality of image signals are stored in each page according to the frame memory structure; and computing a signal storage address by combining image acquiring information by bits, and accessing a frame memory map to write or read an image signal by pages.

Abstract: A video encoding apparatus and method using a pipeline technique with a variable time slot are provided. More particularly, a video encoding apparatus and method capable of shortening a video encoding time by variably adjusting lengths of time slots when an H.264 video encoding process is performed in a pipeline structure are provided. The video encoding apparatus includes a plurality of functional blocks that perform video encoding steps based on an H.264 standard for macroblocks configuring input digital video signals in a pipeline structure, and a controller that controls lengths of time slots configuring the pipeline structure based on done signals received from the plurality of functional blocks. Lengths of time slots can be adjusted according to operation times of video encoding steps using done signals generated from functional blocks, thereby preventing unnecessary power consumption and delays when using a fixed-length time slot.

Abstract: Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.