Abstract: A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.

Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

Abstract: A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.

Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

Abstract: A device, for protecting against electrostatic discharge, structured as a PNPN junction, includes: first and second conductivity type regions formed in a substrate, contacting each other; a first diffusion layer of second conductivity type dopants formed in the first conductivity type region and electrically connected to an anode; a second diffusion layer of first conductivity type dopants formed in the second conductivity type region and electrically connected to a cathode; and at least one of (A) a third diffusion layer of first conductivity type dopants formed in the first conductivity type region between the first diffusion layer and the second conductivity type region and electrically connected to the anode through a first external resistor, and a (B) fourth diffusion layer of second conductivity type dopants formed in the second conductivity type region between the second diffusion layer and the first conductivity type region and electrically connected to the cathode through a second external resistor.

Abstract: Magnetic random access memories (MRAM) are disclosed. The MRAM stores multi-level data by electronically coupling one diode and a plurality of resistance transfer devices, thereby improving a storage capacity and property of the device and achieving high integration thereof. The MRAM may also include a diode, a word line electrically coupled to the diode, a connection layer electrically coupled to the diode; and a plurality of connection pairs each comprising a resistance transfer device and a bit line electrically coupled to the resistance transfer device. One of the connection pairs may be formed on the connection layer, and the bit line of another connection pair may be perpendicular to the bit line of the first connection pair.

Abstract: Magnetic random access memorys (MRAM) are disclosed. The MRAMs store multi-level data by connecting one diode and a plurality of resistance transfer devices, thereby improving a storage capacity and property of the device and achieving high integration thereof.