Patents by Inventor Kyoung-Su Choi

Kyoung-Su Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10862033
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyoung Su Choi
  • Publication number: 20200168795
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Inventor: Kyoung Su CHOI
  • Patent number: 10593878
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyoung Su Choi
  • Publication number: 20190181341
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.
    Type: Application
    Filed: August 21, 2018
    Publication date: June 13, 2019
    Inventor: Kyoung Su CHOI
  • Publication number: 20150200358
    Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof.
    Type: Application
    Filed: April 25, 2014
    Publication date: July 16, 2015
    Applicant: SK hynix Inc.
    Inventors: Se Hun KANG, Jin Ha KIM, Kang Sik CHOI, Deok Sin KIL, Gyu Hyun KIM, Kyoung Su CHOI, Sung Bin HONG, Jung Won SEO
  • Patent number: 6433184
    Abstract: The present invention relates to polyamide-imides having head-to-tail backbone and more particularly, to polyamide-imimdes having head-to-tail ragularity to provide excellent heat and chemical resistance, physical and mechanical properties, processability, and gas permeability and selectivity.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: August 13, 2002
    Assignee: Korea Research Institute of Chemical Technology
    Inventors: Kil-Yeong Choi, Jae Heung Lee, Young-Taik Hong, Moon Young Jin, Kyoung-Su Choi, Ho-Jin Park