Abstract: A buffer circuit includes an amplifier circuit amplifying a difference between an input signal and a reference signal, providing a branch current that varies with a duty cycle of the input signal, and outputting a preliminary output signal on the basis of the amplified difference. The buffer circuit also includes a charge pump circuit charging/discharging a control node in response to the branch current to provide a control signal. The buffer circuit also includes a driver circuit configured to control pull-up strength and pull-down strength for the preliminary output signal based on control signal to thereby correct the duty cycle of the preliminary output signal in relation to a target duty cycle.

Abstract: A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. Accordingly, a failure of a coarse locking may be prevented thus facilitating improved circuit performance.

Abstract: A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance.

Abstract: A buffer circuit includes an amplifier circuit amplifying a difference between an input signal and a reference signal, providing a branch current that varies with a duty cycle of the input signal, and outputting a preliminary output signal on the basis of the amplified difference. The buffer circuit also includes a charge pump circuit charging/discharging a control node in response to the branch current to provide a control signal. The buffer circuit also includes a driver circuit configured to control pull-up strength and pull-down strength for the preliminary output signal based on control signal to thereby correct the duty cycle of the preliminary output signal in relation to a target duty cycle.

Abstract: A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance.