Abstract: A method for changing a route when an error occurs in an autonomous driving AI includes collecting error information of the AI when an error of the AI has occurred, extracting, from a storage, past error information about a same kind of AI as that of the AI based on the error information of the AI, generating an error analysis result based on the past error information, generating an error analysis result message based on the error analysis result, and determining whether the driving of the autonomous driving vehicle needs to be stopped based on the error analysis result message.

Abstract: The present invention relates to a compound capable of lowering the flammability of a non-aqueous electrolyte when included in the non-aqueous electrolyte and improving the life properties of a battery by forming an electrode-electrolyte interface which is stable at high temperatures and low in resistance, and relates to a compound represented by Formula I descried herein, a non-aqueous electrolyte solution and a lithium secondary battery both including the compound, n, m, Ak, and X are described herein.

Abstract: Disclosed is a composite for forming a coacervate interfacial film. The composite for forming the coacervate interfacial film contains a cationic hectorite nanoplate-shaped particle structure containing a hectorite nanoplate-shaped particle and a cationic surfactant coupled to a surface of the hectorite nanoplate-shaped particle, and an anionic cellulose nanofibril containing an anionic functional group in at least a portion thereof, in which the composite may form the coacervate interfacial film at an interface of an oil phase and a water phase through electrostatic interaction between the cationic surfactant and the anionic functional group.

Abstract: A method of automatically detecting a dynamic object recognition error in an autonomous vehicle is provided. The method includes parsing sensor data obtained by frame units from a sensor device equipped in an autonomous vehicle to generate raw data by using a parser, analyzing the raw data to output a dynamic object detection result by using a dynamic object recognition model, determining that detection of a dynamic object recognition error succeeds by using an error detector when the dynamic object detection result satisfies an error detection condition, and storing the raw data and the dynamic object detection result by using a non-volatile memory when the detection of the dynamic object recognition error succeeds.

Abstract: A memory device, a host device and a memory system are provided. The memory device may include a plurality of storage units configured to store data, and at least one device controller configured to, receive a read command from at least one host device and to read data stored in the plurality of storage units in response to the read command, the at least one host device including at least one host memory including a plurality of HPB (high performance boosting) entry storage regions, and provide the at least one host device with a response command, the response command indicating an activation or deactivation of the plurality of HPB entry storage regions, the response command including HPB entry type information which indicates a HPB entry type of the HPB entry storage region.

Abstract: The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.

Abstract: Disclosed herein is a porous separator for electrochemical devices, configured to guarantee electrical insulation between a positive electrode and a negative electrode, wherein the porous separator includes no polyolefin substrate, and includes inorganic particles, a binder for coupling between the inorganic particles, and a crosslinking agent.

Abstract: An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.

Abstract: A preparation process of 5-ethylidene-2-norbornene, including: introducing dicyclopentadiene into a dicyclopentadiene decomposition reactor to thermally decompose the dicyclopentadiene; introducing a product of the above step into a cyclopentadiene purification tower; introducing 1,3-butadiene, a solvent, and cyclopentadiene separated from the top of the cyclopentadiene purification tower into a Diels-Alder reactor to react the same; introducing a product of the immediate above step into a 1,3-butadiene removal tower to recover 1,3-butadiene from the top; introducing a mixture at the bottom of the 1,3-butadiene removal tower into a desolvation tower, and recycling a solvent and unreacted raw materials recovered from the top of the desolvation tower to the dicyclopentadiene decomposition reactor; introducing a mixture at the bottom of the desolvation tower into a 5-vinyl-2-norbornene separation tower to separate 5-vinyl-2-norbornene; and introducing the 5-vinyl-2-norbornene into an isomerization reactor to rea

Abstract: The present invention provides an anti-PD-L1/anti-CD47 bispecific antibody and a preparation method therefor. The antibody has characteristics of a natural IgG, and is a highly stable heterodimeric form without heavy and light chain mismatching. The bispecific antibody can bind two target molecules at the same time and has a smaller side effect.

Abstract: Provided are an anti-PD-L1/anti-4-1BB natural antibody structure-like heterodimeric form bispecific antibody and a preparation thereof. Specifically, provided are an anti-PD-L1/anti-4-1BB bispecific antibody that has natural IgG features, that has no mismatch between heavy and light chains and that is in the form of a highly stable heterodimer, as well as a preparation method therefor. The bispecific antibody can simultaneously bind two target molecules and is more effective in treating complex diseases and has fewer side effects.

Abstract: A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

Abstract: The present invention relates to a human Lefty A protein variant with improved productivity and stability, a fusion protein comprising the protein variant, and a composition for preventing and/or treating neuromuscular disease comprising the protein variant or the fusion protein. According to the present invention, a human Lefty A protein variant and a fusion protein comprising the variant are constructed, which have better stability than naturally occurring human Lefty A protein, and thus are expressed at high levels and produced in high yield in animal cells. In addition, administration of the constructed human Lefty A protein variant or fusion protein can restore the nerve and motor functions of nerve disease model animals. Accordingly, the use of the human Lefty A protein variant or fusion protein can effectively prevent or treat various nerve diseases and muscle diseases.

Abstract: Disclosed is a washing machine including a drying function. Here, a height of a bottom end of a dryer disposed above a tub is lower than a height of a top end of the tub to have a space for integrating other devices having additional functions above the tub.

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

Abstract: A method of fabricating an interconnection line of a semiconductor device includes forming a via and a lower interconnection trench in a first interlayer insulating layer, an etch stop layer, and a second interlayer insulating layer on a substrate, forming a lower diffusion barrier layer, a lower seed layer, and a lower interconnection layer inside the via and the lower interconnection trench, planarizing the lower interconnection layer using a chemical mechanical polishing (CMP) process to form a contact plug and a lower interconnection line, depositing a third interlayer insulating layer on top of a second interlayer insulating pattern and the lower interconnection line, forming an upper interconnection trench in the third interlayer insulating layer, forming an upper diffusion barrier layer, an upper seed layer, and an upper interconnection layer inside the upper interconnection trench, and planarizing the upper interconnection layer using a CMP process to form an upper interconnection line.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.