Patents by Inventor Kyoung-Wook Park
Kyoung-Wook Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8385109Abstract: A nonvolatile memory device includes a cell array including a plurality of phase change memory cells, a switching unit configured to select any one of the plurality of phase change memory cells, a clamping unit coupled between the switching unit and a sensing line and configured to adjust an amount of a clamping current flowing through the sensing line, a program switching unit configured to couple the switching unit to the sensing line during a program operation, a voltage driving unit configured to supply the sensing line with a write voltage corresponding to data to be written during the program operation, and supply the sensing line with a constant read voltage during a data sensing operation, and a sense amplifier configured to compare and amplify a voltage of the sensing line and a preset read reference voltage.Type: GrantFiled: June 25, 2010Date of Patent: February 26, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Wook Park
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Patent number: 8363498Abstract: A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat, a column switching unit configured to select any one of bit lines from among the plurality of bit lines according to a column selection signal, and selectively control a connection between the selected bit line and a global bit line, and a discharge unit, in an active mode in which the read or write operation is achieved, configured to discharge the remaining bit lines other than the selected bit line from among the plurality of bit lines in response to a bit line discharge signal.Type: GrantFiled: June 25, 2010Date of Patent: January 29, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Wook Park
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Patent number: 8325514Abstract: A phase change memory device includes a plurality of programming current driving blocks each of which is configured to provide a corresponding phase change memory cell with a programming current corresponding to input data and a programming current adjusting block commonly connected to the plurality of programming current driving blocks and configured to generate a control voltage to adjust the programming current.Type: GrantFiled: April 29, 2009Date of Patent: December 4, 2012Assignee: Hynix Semiconductor, Inc.Inventor: Kyoung-Wook Park
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Publication number: 20120081954Abstract: A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of phase change memory cells are vertically stacked in a cell array area.Type: ApplicationFiled: December 31, 2010Publication date: April 5, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kyoung Wook PARK
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Patent number: 8077507Abstract: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.Type: GrantFiled: February 17, 2011Date of Patent: December 13, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyoung-Wook Park
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Publication number: 20110292749Abstract: A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat, a column switching unit configured to select any one of bit lines from among the plurality of bit lines according to a column selection signal, and selectively control a connection between the selected bit line and a global bit line, and a discharge unit, in an active mode in which the read or write operation is achieved, configured to discharge the remaining bit lines other than the selected bit line from among the plurality of bit lines in response to a bit line discharge signal.Type: ApplicationFiled: June 25, 2010Publication date: December 1, 2011Applicant: Hynix Semiconductor Inc.Inventor: Kyoung Wook PARK
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Publication number: 20110261610Abstract: A nonvolatile memory device includes a cell array including a plurality of phase change memory cells, a switching unit configured to select any one of the plurality of phase change memory cells, a clamping unit coupled between the switching unit and a sensing line and configured to adjust an amount of a clamping current flowing through the sensing line, a program switching unit configured to couple the switching unit to the sensing line during a program operation, a voltage driving unit configured to supply the sensing line with a write voltage corresponding to data to be written during the program operation, and supply the sensing line with a constant read voltage during a data sensing operation, and a sense amplifier configured to compare and amplify a voltage of the sensing line and a preset read reference voltage.Type: ApplicationFiled: June 25, 2010Publication date: October 27, 2011Applicant: Hynix Semiconductor Inc.Inventor: Kyoung Wook PARK
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Patent number: 7983077Abstract: A phase change memory apparatus is presented. The phase change memory apparatus includes a phase change memory cell, a sense amplifier, and a voltage selecting unit. The sense amplifier is configured to differentially amplify a current that through the memory cell and a comparison voltage. The voltage selecting unit is configured to provide a reference voltage as the comparison voltage when performing a normal read function and to selectively provide either a first voltage level or a second voltage level as the comparison voltage in accordance with data when performing a verify read function.Type: GrantFiled: June 30, 2009Date of Patent: July 19, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Wook Park
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Publication number: 20110141800Abstract: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.Type: ApplicationFiled: February 17, 2011Publication date: June 16, 2011Inventor: Kyoung-Wook PARK
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Patent number: 7952908Abstract: A multi-level sensing apparatus of the non-volatile memory includes a first sense amplifier configured to compare a first reference voltage with a read data of a bit line and amplify a comparison result to generate a first output; a reference voltage selector configured to select one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output; a second sense amplifier configured to compare the fourth reference voltage with the read data of the bit line and amplify a comparison result to generate a second output; and a decoder configured to decode the first and second outputs to output a sensing data.Type: GrantFiled: May 6, 2009Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyoung-Wook Park
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Patent number: 7916525Abstract: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.Type: GrantFiled: December 29, 2008Date of Patent: March 29, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyoung-Wook Park
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Patent number: 7894281Abstract: A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about a sub-block where a column line of the defective memory cell is arranged, and the redundancy column activation signal, controls whether or not to activate a global IO line connected to an IO pad of the sub-block.Type: GrantFiled: July 22, 2008Date of Patent: February 22, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyoung-Wook Park
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Publication number: 20100290275Abstract: A phase change memory apparatus is presented. The phase change memory apparatus includes a phase change memory cell, a sense amplifier, and a voltage selecting unit. The sense amplifier is configured to differentially amplify a current that through the memory cell and a comparison voltage. The voltage selecting unit is configured to provide a reference voltage as the comparison voltage when performing a normal read function and to selectively provide either a first voltage level or a second voltage level as the comparison voltage in accordance with data when performing a verify read function.Type: ApplicationFiled: June 30, 2009Publication date: November 18, 2010Inventor: Kyoung Wook PARK
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Patent number: 7830712Abstract: A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to selectively activate one of the plurality of buffer stages when a burst mode as a synchronous mode is activated.Type: GrantFiled: December 8, 2008Date of Patent: November 9, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kyoung-Wook Park
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Publication number: 20100281203Abstract: A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit.Type: ApplicationFiled: June 22, 2009Publication date: November 4, 2010Inventors: Ji-Hyae Bae, Kyoung-Wook Park
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Publication number: 20100165718Abstract: A multi-level sensing apparatus of the non-volatile memory includes a first sense amplifier configured to compare a first reference voltage with a read data of a bit line and amplify a comparison result to generate a first output; a reference voltage selector configured to select one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output; a second sense amplifier configured to compare the fourth reference voltage with the read data of the bit line and amplify a comparison result to generate a second output; and a decoder configured to decode the first and second outputs to output a sensing data.Type: ApplicationFiled: May 6, 2009Publication date: July 1, 2010Inventor: Kyoung-Wook Park
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Publication number: 20100149861Abstract: A phase change memory device includes a plurality of programming current driving blocks each of which is configured to provide a corresponding phase change memory cell with a programming current corresponding to input data and a programming current adjusting block commonly connected to the plurality of programming current driving blocks and configured to generate a control voltage to adjust the programming current.Type: ApplicationFiled: April 29, 2009Publication date: June 17, 2010Inventor: Kyoung-Wook PARK
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Publication number: 20100149859Abstract: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.Type: ApplicationFiled: December 29, 2008Publication date: June 17, 2010Inventor: Kyoung-Wook PARK
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Publication number: 20090201735Abstract: A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to selectively activate one of the plurality of buffer stages when a burst mode as a synchronous mode is activated.Type: ApplicationFiled: December 8, 2008Publication date: August 13, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventor: Kyoung-Wook Park
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Publication number: 20090168570Abstract: A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about a sub-block where a column line of the defective memory cell is arranged, and the redundancy column activation signal, controls whether or not to activate a global IO line connected to an IO pad of the sub-block.Type: ApplicationFiled: July 22, 2008Publication date: July 2, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventor: Kyoung Wook Park