Patents by Inventor Kyoung Wook Seok

Kyoung Wook Seok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985242
    Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Publication number: 20200286988
    Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10601331
    Abstract: An AC-to-DC converter circuit includes DC-to-DC converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor. Each of the synchronous rectifiers includes a bipolar transistor and a diode whose anode is coupled to the transistor collector and whose cathode is coupled to the transistor emitter. The current splitting inductors provide the necessary base current to the bipolar transistors at the appropriate times such that the bipolar transistors operate as synchronous rectifiers.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: March 24, 2020
    Assignee: Littlefuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10535760
    Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
    Type: Grant
    Filed: January 21, 2018
    Date of Patent: January 14, 2020
    Assignee: LITTELFUSE, INC.
    Inventor: Kyoung Wook Seok
  • Patent number: 10446641
    Abstract: A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped P? type columns, a floating ring-shaped P? type column that surrounds the set of strip-shaped P? type columns, and a set of ring-shaped P? type columns that surrounds the floating ring-shaped P? type column. A source metal is disposed above portions of the charge compensation region. The source metal contacts each of the strip-shaped P? type columns and each of the ring-shaped P? type columns. An oxide is disposed between the floating P? type column and the source metal such that the floating P? type column is electrically isolated from the source metal. The device exhibits a breakdown voltage that is 0.2% greater than if the floating P? type column were to contact the source metal.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 15, 2019
    Assignee: LITTELFUSE, INC.
    Inventor: Kyoung Wook Seok
  • Patent number: 10446674
    Abstract: A trench IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a novel waved contour so that it has thinner portions and thicker portions. When the IGBT is on, electrons flow from an N+ emitter, vertically through a channel along a trench sidewall, and to an N? type drift layer. Additional electrons flow through the channel but then pass under the trench, through the floating P well to the floating N+ well, and laterally through the floating N+ well. NPN transistors are located at thinner portions of the floating P type well. The NPN transistors inject electrons from the floating N+ type well down into the N? drift layer. The extra electron injection reduces VCE(SAT). The waved contour can be made without adding any masking step to an IGBT manufacturing process.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 15, 2019
    Assignee: LITTELFUSE, INC.
    Inventor: Kyoung Wook Seok
  • Patent number: 10424677
    Abstract: An inverse diode die is “fast” (i.e., has a small peak reverse recovery current) due to the presence of a novel topside P+ type charge carrier extraction region and a lightly-doped bottomside transparent anode. During forward conduction, the number of charge carriers in the N? type drift region is reduced due to holes being continuously extracted by an electric field set up by the P+ type charge carrier extraction region. Electrons are extracted by the transparent anode. When the voltage across the device is then reversed, the magnitude of the peak reverse recovery current is reduced due to there being a smaller number of charge carriers that need to be removed before the diode can begin reverse blocking mode operation. Advantageously, the diode is fast without having to include lifetime killers or otherwise introduce recombination centers. The inverse diode therefore has a desirably small reverse leakage current.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 24, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Publication number: 20190252990
    Abstract: An AC-to-DC converter circuit includes DC-to-DC converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor. Each of the synchronous rectifiers includes a bipolar transistor and a diode whose anode is coupled to the transistor collector and whose cathode is coupled to the transistor emitter. The current splitting inductors provide the necessary base current to the bipolar transistors at the appropriate times such that the bipolar transistors operate as synchronous rectifiers.
    Type: Application
    Filed: November 30, 2015
    Publication date: August 15, 2019
    Applicant: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10367085
    Abstract: An IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a waved contour with thinner portions and thicker portions. When the device is on, electrons flow laterally from an N+ emitter and through a channel region. Some electrons pass downward, but others pass laterally through the floating N+ well to one of the thinner portions of the floating P type well. The electrons then pass down from the thinner portions into the N? drift layer. Other electrons pass farther through the floating N+ well to subsequent, thinner electron injector portions of the floating P type well and then into the N? drift layer. The extra electron injection afforded by the waved floating well structure reduces VCE(SAT). The waved contour is made without adding any masking step to the IGBT manufacturing process.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 30, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10361276
    Abstract: A trench N-channel field effect transistor has an active area and an edge area. A first pair of parallel-extending deep trenches extends parallel to a side edge of the die. A second pair of parallel-extending deep trenches extends perpendicularly to the side edge, toward the side edge, so that each trench of the second pair terminates into the inside deep trench of the first pair. An embedded field plate structure is embedded in these trenches. A plurality of floating P type well regions is disposed entirely between the second pair of deep trenches, between the active area and the inside deep trench of the first pair. Using this edge area structure, the breakdown voltage BVDSS of the overall device is increased because the breakdown voltage of the edge area is increased as compared to the same structure without the floating P type well regions.
    Type: Grant
    Filed: March 17, 2018
    Date of Patent: July 23, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10319669
    Abstract: A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 11, 2019
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10249716
    Abstract: A combination switch includes an Insulated Gate Bipolar Transistor (IGBT), an anti-parallel diode, and a saturable inductor. The diode and inductor are coupled in series between a collector and an emitter of the IGBT. The inductor is fashioned so that it will come out of saturation when a forward bias current flow through the diode falls below a saturation current level. When the diode current falls (for example, due to another combination switch of a phase leg turning on), the diode current initially falls at a high rate until the inductor current drops to the saturation current level. Thereafter, the diode current falls at a lower rate. The lower rate allows the diode current to have a soft landing to zero current, thereby eliminating or reducing voltage and/or current spikes that would otherwise occur. Multiple methods of implementing and manufacturing the saturable inductor are disclosed.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 2, 2019
    Assignee: IXYS, LLC
    Inventors: Kyoung Wook Seok, Joseph James Roosma
  • Publication number: 20190067174
    Abstract: A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventor: Kyoung Wook Seok
  • Publication number: 20190067493
    Abstract: An inverse diode die is “fast” (i.e., has a small peak reverse recovery current) due to the presence of a novel topside P+ type charge carrier extraction region and a lightly-doped bottomside transparent anode. During forward conduction, the number of charge carriers in the N-type drift region is reduced due to holes being continuously extracted by an electric field set up by the P+ type charge carrier extraction region. Electrons are extracted by the transparent anode. When the voltage across the device is then reversed, the magnitude of the peak reverse recovery current is reduced due to there being a smaller number of charge carriers that need to be removed before the diode can begin reverse blocking mode operation. Advantageously, the diode is fast without having to include lifetime killers or otherwise introduce recombination centers. The inverse diode therefore has a desirably small reverse leakage current.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10217847
    Abstract: A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 26, 2019
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Publication number: 20180342608
    Abstract: Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication. plants that cannot or typically do not make superjunction MOSFETs.
    Type: Application
    Filed: July 13, 2018
    Publication date: November 29, 2018
    Inventor: Kyoung Wook Seok
  • Patent number: 10062686
    Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P? epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P? type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: August 28, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10038088
    Abstract: Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 31, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10038383
    Abstract: A Low Forward Voltage Rectifier (LFVR) circuit includes a bipolar transistor, a parallel diode, and a capacitive current splitting network. The LFVR circuit, when it is performing a rectifying function, conducts the forward current from a first node to a second node provided that the voltage from the first node to the second node is adequately positive. The capacitive current splitting network causes a portion of the forward current to be a base current of the bipolar transistor, thereby biasing the transistor so that the forward current experiences a low forward voltage drop across the transistor. The LFVR circuit sees use in as a rectifier in many different types of switching power converters, including in flyback, Cuk, SEPIC, boost, buck-boost, PFC, half-bridge resonant, and full-bridge resonant converters. Due to the low forward voltage drop across the LFVR, converter efficiency is improved.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: July 31, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10014852
    Abstract: A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors coupled in series between a first terminal and a second terminal. The HVSTC also has a control terminal for turning on an off the power transistors of the stack. All of the power transistors of the stack turn on together, and turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage. Each power transistor, other than the one most directly coupled to the first terminal, has an associated bipolar transistor. In a static on state of the HVSTC, the bipolar transistors are off. The associated power transistors can therefore be turned on. In a static off state of the HVSTC, the bipolar transistors are conductive (in one example, in the reverse active mode) in such a way that they keep their associated power transistors off.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: July 3, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok