Abstract: Disclosed is a fuel cell system. The fuel cell system of the present invention is characterized by a gas-liquid separator for removing foreign substances in air between a stack and an air supply unit. So the present invention can therefore prevent the foreign substances from being supplied to the stack and improve the function and extend the lifetime of the stack.

Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.

Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.

Abstract: A staircase shaped stacked semiconductor package is presented which includes a substrate, a multiplicity of semiconductor chip modules, a connection member, and conductive members. The substrate has connection pads along an upper surface edge. Each semiconductor chip module includes a first and a second semiconductor chip that oppose each other. The first and second semiconductor chips have respective first and second bonding pads along exposed surfaces. The connection member is placed on an uppermost semiconductor chip module and has first and second terminals electrically connected to the first and second bonding pads via conductive members. The conductive members are also coupled to the connection pads of the substrate.

Abstract: A staircase shaped stacked semiconductor package is presented which includes a substrate, a multiplicity of semiconductor chip modules, a connection member, and conductive members. The substrate has connection pads along an upper surface edge. Each semiconductor chip module includes a first and a second semiconductor chip that oppose each other. The first and second semiconductor chips have respective first and second bonding pads along exposed surfaces. The connection member is placed on an uppermost semiconductor chip module and has first and second terminals electrically connected to the first and second bonding pads via conductive members. The conductive members are also coupled to the connection pads of the substrate.

Abstract: A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.

Abstract: A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.

Abstract: A submicron level dimension reference for use with a scanning electron microscope in a semiconductor device fabrication apparatus. The reference has a first insulating layer with a first pattern formed on a semiconductor wafer substrate. A plurality of contacts are formed between the first pattern of the first insulating layer such that the contacts directly communicate the wafer substrate. The contacts are capable of carrying an electrical charge. An electrically conductive layer is formed over the contacts and the first insulating layer. A second insulating layer with a second pattern is formed over the conductive layer. Electrical charges generated by radiating the scanning electron microscope on the submicron level dimension reference are transferred from the first and second insulating layers to the wafer substrate via the conductive layer and the plurality of contacts.

Abstract: A method for testing a contact opening of a semiconductor device includes the steps of: inspecting a wafer using an in-line scanning electron microscope, comparing a contrast difference of contact opening regions displayed on the scanning electron microscope, and determining whether the processes for forming the contact openings have been performed correctly based on results of the comparison step. The test method may be performed after any of a contact photolithography process, contact etching process, or conductive layer etching process.