Abstract: A memory controller and a storage device including the same are provided. The memory controller includes memory channel controllers configured to perform erase, program, read, erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer spaceaafter the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes a memory channel controller configured to perform erase/program, read, and erase/program suspend operations for a flash memory, a flash translation layer configured to control an operation of the memory channel controller by receiving a write/read command, and transmit a completion for the write/read command, a host interface configured to receive the write/read command from a host, transmit the write/read command to the flash translation layer, receive the completion from the flash translation layer, and calculate a write/read latency for the write/read command based on the completion, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the calculated write/read latency, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes memory channel controllers configured to perform erase, program, read, erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer spaceaafter the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes a memory channel controller configured to perform erase/program, read, and erase/program suspend operations for a flash memory, a flash translation layer configured to control an operation of the memory channel controller by receiving a write/read command, and transmit a completion for the write/read command, a host interface configured to receive the write/read command from a host, transmit the write/read command to the flash translation layer, receive the completion from the flash translation layer, and calculate a write/read latency for the write/read command based on the completion, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the calculated write/read latency, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.