Abstract: Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.

Abstract: A semiconductor package may include a plurality of first semiconductor package mounted on a first region of a first surface of a first circuit board, a plurality of terminals disposed between the plurality of first semiconductor chips on a second region of the first surface of the first circuit board, and at least one second semiconductor chip mounted on a second circuit board connected to the first circuit board through the plurality of terminals.

Abstract: Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

Abstract: A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

Abstract: Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.

Abstract: Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

Abstract: A semiconductor package may include a plurality of first semiconductor package mounted on a first region of a first surface of a first circuit board, a plurality of terminals disposed between the plurality of first semiconductor chips on a second region of the first surface of the first circuit board, and at least one second semiconductor chip mounted on a second circuit board connected to the first circuit board through the plurality of terminals.

Abstract: A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

Abstract: A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.

Abstract: A multi-layer printed circuit board (PCB) and a method for fabricating the same are provided. The multi-layer printed circuit board may include a first film and a first insulation layer. The first film may include a first via therein and the first film may further include a first conductive pattern on an upper surface thereof and the first conductive layer may be electrically connected to the first via. The first insulation layer may be on the upper surface of the first film and the first insulation layer may include a second via therein and a second conductive pattern on an upper surface thereof and the second conductive pattern may be electrically connected to the second via. The second via may be electrically connected to the first conductive pattern.

Abstract: A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure.

Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Abstract: A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.

Abstract: Provided is an electromagnetic interference (EMI) removing device for active reduction of electromagnetic interference and a semiconductor package including the same. The EMI removing device may include a film substrate having an antenna pattern configured to generate a second electromagnetic wave, which may have substantially the same frequency band, modulation mode, and directivity as a first electromagnetic wave generated by a first semiconductor chip and a phase opposite to a phase of the first electromagnetic wave.

Abstract: Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate tine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.

Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Abstract: A flexible substrate used in a semiconductor package, a method of manufacturing the same, and a semiconductor package including the flexible substrate. A circuit pattern forming region is formed in an insulating substrate with a dented shape and a circuit pattern formed of a metallic material is formed in the circuit pattern forming region.