Abstract: A training data service system for operation scope-oriented autonomous driving shuttle includes a communication module configured to collect an autonomous driving data set from an autonomous driving vehicle to construct training data and distribute the training data to an autonomous driving shuttle, a memory configured to store a program for construction of the training data, and a processor configured to generate query data including road shape information, road attribute information, traffic environment information, and collection sensor information by executing the program stored in the memory, detect data satisfying a condition corresponding to the query data from a previously collected autonomous driving data set, construct training data for the autonomous driving shuttle, based on the detected data, and distribute the constructed training data to a corresponding autonomous driving shuttle.

Abstract: A semiconductor device includes a substrate that includes a first surface and a second surface, a first source/drain pattern disposed on the first surface of the substrate, a second source/drain pattern disposed on the first surface of the, a first source/drain contact disposed on the first source/drain pattern and connected to the first source/drain pattern, a second source/drain contact disposed on the second source/drain pattern and connected to the second source/drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source/drain contact, a second contact connection via that connects the rear wiring line with the second source/drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

Abstract: A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.

Abstract: A negative electrode for a lithium secondary battery includes: a negative electrode active layer provided on at least one surface of a negative electrode current collector, and including a negative electrode active material; and a coating layer disposed on the negative electrode active layer. The coating layer contains silicon-containing particles, aluminum-containing particles and a dispersant, and a volume resistance of the coating layer is about 1.0×10?4 ?·cm to 1.0 ?·cm.

Abstract: Disclosed are a method and apparatus for random access using random beam-switching in a wireless network environment. The random access method using random beam-switching in a wireless network environment includes selecting a given preamble when receiving a synchronization signal block from a base station, transmitting, to the base station, a first message including the selected preamble by using a sequential beam-sweeping method, transmitting a third message for a connection request for uplink data transmission when receiving, from the base station, a second message responding to the transmitted first message, and completing a random access channel operation when receiving a fourth message responding to the transmitted third message.

Abstract: A semiconductor device is provided.

Abstract: Provided are an antibody specifically binding to PD-L1 and an antigen-binding fragment thereof. The antibody and the antigen-binding fragment thereof have high specificity and stability, can specifically block a PD-L1-SIPR? pathway, do not cause hemagglutination within a certain concentration range, and thus can significantly suppress tumor growth in vivo.

Abstract: A semiconductor device includes an active pattern on a first surface of a substrate and extending in a first direction, a field insulating film on the first surface and a side surface of the active pattern, a gate structure on the active pattern and field insulating film and extending in a second direction intersecting the first direction, a source/drain area on a side surface of the gate structure and contacting the active pattern, and a through-contact extending in a third direction perpendicular to the first and second directions and extending through the field insulating film. The device further includes a buried pattern in the substrate contacting the through-contact, a backside wiring structure on a second surface of the substrate and electrically connected to the buried pattern, and a heat-dissipating structure in the substrate adjacent to the buried pattern. The heat-dissipating structure fills a trench extending from the second surface into the substrate.

Abstract: A semiconductor device includes a substrate that has first and second surfaces opposite to each other in a first direction, a first fin-type pattern that protrudes in the first direction from the first surface of the substrate and extends in a second direction, a first source/drain pattern on the first fin-type pattern, a first source/drain contact on the first source/drain pattern, a contact connection via that extends in the first direction and is electrically connected to the first source/drain contact, a buried conductive pattern that is in the substrate, is electrically connected to the contact connection via, and has first and second surfaces opposite to each other in the first direction, the first surface of the buried conductive pattern facing the first source/drain contact, and first buried insulating liners that extend along sidewalls and along the first surface of the buried conductive pattern.

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a power delivery network layer; an insulating layer on the power delivery network layer and having an opening therein; a semiconductor layer filling the opening and covering the insulating layer; a first through-via extending through the semiconductor layer and electrically connected to the power delivery network layer; a second through-via extending through the insulating layer and the semiconductor layer and electrically connected to the power delivery network layer; a logic element on the semiconductor layer and electrically connected to the first through-via; and a passive element on the semiconductor layer and electrically connected to the second through-via.

Abstract: The present invention provides an anti-PD-L1/anti-CD47 bispecific antibody and a preparation method therefor. The antibody has characteristics of a natural IgG, and is a highly stable heterodimeric form without heavy and light chain mismatching. The bispecific antibody can bind two target molecules at the same time and has a smaller side effect.

Abstract: Provided are an anti-PD-L1/anti-4-1BB natural antibody structure-like heterodimeric form bispecific antibody and a preparation thereof. Specifically, provided are an anti-PD-L1/anti-4-1BB bispecific antibody that has natural IgG features, that has no mismatch between heavy and light chains and that is in the form of a highly stable heterodimer, as well as a preparation method therefor. The bispecific antibody can simultaneously bind two target molecules and is more effective in treating complex diseases and has fewer side effects.

Abstract: A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

Abstract: The present invention relates to a human Lefty A protein variant with improved productivity and stability, a fusion protein comprising the protein variant, and a composition for preventing and/or treating neuromuscular disease comprising the protein variant or the fusion protein. According to the present invention, a human Lefty A protein variant and a fusion protein comprising the variant are constructed, which have better stability than naturally occurring human Lefty A protein, and thus are expressed at high levels and produced in high yield in animal cells. In addition, administration of the constructed human Lefty A protein variant or fusion protein can restore the nerve and motor functions of nerve disease model animals. Accordingly, the use of the human Lefty A protein variant or fusion protein can effectively prevent or treat various nerve diseases and muscle diseases.

Abstract: Disclosed is a washing machine including a drying function. Here, a height of a bottom end of a dryer disposed above a tub is lower than a height of a top end of the tub to have a space for integrating other devices having additional functions above the tub.

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

Abstract: A method of fabricating an interconnection line of a semiconductor device includes forming a via and a lower interconnection trench in a first interlayer insulating layer, an etch stop layer, and a second interlayer insulating layer on a substrate, forming a lower diffusion barrier layer, a lower seed layer, and a lower interconnection layer inside the via and the lower interconnection trench, planarizing the lower interconnection layer using a chemical mechanical polishing (CMP) process to form a contact plug and a lower interconnection line, depositing a third interlayer insulating layer on top of a second interlayer insulating pattern and the lower interconnection line, forming an upper interconnection trench in the third interlayer insulating layer, forming an upper diffusion barrier layer, an upper seed layer, and an upper interconnection layer inside the upper interconnection trench, and planarizing the upper interconnection layer using a CMP process to form an upper interconnection line.