Patents by Inventor Kyouzou Kanamoto

Kyouzou Kanamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060054940
    Abstract: The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1, the channel layer 4 with thickness 1000 ? or less on the drain layer, the source layer 5 consisting of an epitaxial single crystal layer on the channel layer 4, and the insulated-gates 6 and 7 on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 ? or less is accurately controlled using the molecular layer epitaxial method and the channel layer 4 is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 16, 2006
    Applicants: Incorporated Administrative Agency, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Toru Kurabayashi, Toru Oizumi, Kyouzou Kanamoto, Jun-ichi Nishizawa
  • Patent number: 6977406
    Abstract: The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1, the channel layer 4 with thickness 1000 ? or less on the drain layer, the source layer 5 consisting of an epitaxial single crystal layer on the channel layer 4, and the insulated-gates 6 and 7 on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 ? or less is accurately controlled using the molecular layer epitaxial method and the channel layer 4 is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: December 20, 2005
    Assignees: National Institute of Information and Communications Technology, Incorporated Administrative Agency, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Toru Kurabayashi, Toru Oizumi, Kyouzou Kanamoto, Jun-ichi Nishizawa
  • Publication number: 20040178442
    Abstract: The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1, the channel layer 4 with thickness 1000 Å or less on the drain layer, the source layer 5 consisting of an epitaxial single crystal layer on the channel layer 4, and the insulated-gates 6 and 7 on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 Å or less is accurately controlled using the molecular layer epitaxial method and the channel layer 4 is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.
    Type: Application
    Filed: October 24, 2003
    Publication date: September 16, 2004
    Inventors: Toru Kurabayashi, Toru Oizumi, Kyouzou Kanamoto, Jun-ichi Nishizawa