Abstract: A maximum/minimum value output circuit that selectively outputs a maximum/minimum value signal from plural input signals is disclosed. The maximum/minimum value output circuit includes plural input transistors having bases that are configured to input differing input signals, and collector-emitter structures that are connected through parallel connection; a current mirror circuit that outputs a current according to currents at the input transistors; and an output transistor having a collector-emitter structure to which a current is supplied according to the output current of the current mirror circuit, and a base that outputs a signal corresponding to a maximum or minimum level input signal of the differing input signals input to the bases of the input transistors.