Patents by Inventor Kyoya Nitta
Kyoya Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8344454Abstract: An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.Type: GrantFiled: March 16, 2011Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Kyoya Nitta, Yutaka Hoshino
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Publication number: 20120302061Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.Type: ApplicationFiled: August 1, 2012Publication date: November 29, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki ARIE, Nobuaki UMEMURA, Nobuyoshi HATTORI, Nobuto NAKANISHI, Kimio HARA, Kyoya NITTA, Makoto ISHIKAWA
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Patent number: 8319265Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: October 16, 2009Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 8242605Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.Type: GrantFiled: June 8, 2010Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Arie, Nobuaki Umemura, Nobuyoshi Hattori, Nobuto Nakanishi, Kimio Hara, Kyoya Nitta, Makoto Ishikawa
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Publication number: 20120199905Abstract: A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.Type: ApplicationFiled: February 2, 2012Publication date: August 9, 2012Inventor: Kyoya NITTA
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Publication number: 20110248344Abstract: An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.Type: ApplicationFiled: March 16, 2011Publication date: October 13, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kyoya NITTA, Yutaka HOSHINO
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Publication number: 20110024820Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Inventors: Takeshi SAKAI, Yasushi ISHII, Tsutomu OKAZAKI, Masaru NAKAMICHI, Toshikazu MATSUI, Kyoya NITTA, Satoru MACHIDA, Munekatsu NAKAGAWA, Yuichi TSUKADA
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Patent number: 7863135Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: February 16, 2010Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Publication number: 20100327349Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.Type: ApplicationFiled: June 8, 2010Publication date: December 30, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki ARIE, Nobuaki UMEMURA, Nobuyoshi HATTORI, Nobuto NAKANISHI, Kimio HARA, Kyoya NITTA, Makoto ISHIKAWA
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Publication number: 20100144108Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: February 16, 2010Publication date: June 10, 2010Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Publication number: 20100038700Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: October 16, 2009Publication date: February 18, 2010Inventors: Tsutomu OKAZAKI, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 7663176Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: May 2, 2008Date of Patent: February 16, 2010Assignee: Renesas Technology Corp.Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7636253Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: January 16, 2009Date of Patent: December 22, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20090122609Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: January 16, 2009Publication date: May 14, 2009Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATA, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 7502257Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: May 1, 2007Date of Patent: March 10, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20080203466Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Publication number: 20080206975Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7371631Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: June 29, 2005Date of Patent: May 13, 2008Assignee: Renesas Technology Corp.Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Publication number: 20070201272Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: May 1, 2007Publication date: August 30, 2007Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 7245531Abstract: Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween.Type: GrantFiled: August 8, 2005Date of Patent: July 17, 2007Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui