Patents by Inventor Kyran Wilfred Fey, Jr.

Kyran Wilfred Fey, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Backplane interface sets
    Patent number: 10901932
    Abstract: An example device in accordance with an aspect of the present disclosure includes at least one interface set, including a first interface, at least one second interface, and at least one third interface. A first portion of the first interface is coupled to a second portion of the at least one second interface. A second portion of the first interface is coupled to a first portion of the at least one third interface. The first portion of the first interface is isolated from the second portion of the first interface, the first portion of the second interface is isolated from the second portion of the second interface, and the first portion of the third interface is isolated from the second portion of the third interface.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 26, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brian T Purcell, David M Koonce, Barry L Olawsky, Michael White, Quoc Hung C Vu, Kyran Wilfred Fey, Jr.
  • BACKPLANE INTERFACE SETS
    Publication number: 20170052919
    Abstract: An example device in accordance with an aspect of the present disclosure includes at least one interface set, including a first interface, at least one second interface, and at least one third interface. A first portion of the first interface is coupled to a second portion of the at least one second interface. A second portion of the first interface is coupled to a first portion of the at least one third interface. The first portion of the first interface is isolated from the second portion of the first interface, the first portion of the second interface is isolated from the second portion of the second interface, and the first portion of the third interface is isolated from the second portion of the third interface.
    Type: Application
    Filed: April 23, 2014
    Publication date: February 23, 2017
    Inventors: Brian T Purcell, David M Koonce, Barry L Olawsky, Michael White, Quoc Hung C Vu, Kyran Wilfred Fey, JR.
  • High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors
    Patent number: 5845060
    Abstract: A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: December 1, 1998
    Assignee: Tandem Computers, Incorporated
    Inventors: Richard Alan Vrba, James Stevens Klecka, Kyran Wilfred Fey, Jr., Larry Leonard Lamano, Nikhil A. Mehta