Patents by Inventor Kyu-Baik Chang

Kyu-Baik Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321334
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10714473
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Publication number: 20200066720
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10504894
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 9798849
    Abstract: A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG EELECTRONICS CO., LTD.
    Inventors: Jae-Pil Shin, Chang-Woo Kang, Jong-Won Kim, Ho-Joon Lee, Kyu-Baik Chang, Won-Young Chung
  • Patent number: 9773785
    Abstract: A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: September 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu Baik Chang, Byoung Hak Hong, Yoon Suk Kim, Seung Hyun Song
  • Patent number: 9711505
    Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Hak Hong, Bon-Woong Koo, Sung-Il Park, Kyu-Baik Chang, Keun-Hwi Cho, Dae-Won Ha
  • Patent number: 9698154
    Abstract: A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Sung Lim, Kyu Baik Chang, Sung Hoi Hur, Woo Jung Kim
  • Publication number: 20170162566
    Abstract: A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.
    Type: Application
    Filed: July 26, 2016
    Publication date: June 8, 2017
    Inventors: Kyu Baik CHANG, Byoung Hak HONG, Yoon Suk KIM, Seung Hyun SONG
  • Publication number: 20170162568
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 8, 2017
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Publication number: 20170040335
    Abstract: A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.
    Type: Application
    Filed: May 31, 2016
    Publication date: February 9, 2017
    Inventors: Joon Sung LIM, Kyu Baik CHANG, Sung Hoi HUR, Woo Jung KIM
  • Publication number: 20170033217
    Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.
    Type: Application
    Filed: April 8, 2016
    Publication date: February 2, 2017
    Inventors: BYOUNG-HAK HONG, BON-WOONG KOO, SUNG-IL PARK, KYU-BAIK CHANG, KEUN-HWI CHO, DAE-WON HA
  • Patent number: 9548316
    Abstract: A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Sung Lim, Jang-Gn Yun, Sunghoon Bae, Jaesun Yun, Kyu-Baik Chang
  • Publication number: 20160163730
    Abstract: A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 9, 2016
    Inventors: JOON-SUNG LIM, JANG-GN YUN, SUNGHOON BAE, JAESUN YUN, KYU-BAIK CHANG
  • Publication number: 20160012174
    Abstract: A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.
    Type: Application
    Filed: April 16, 2015
    Publication date: January 14, 2016
    Inventors: Jae-Pil SHIN, Chang-Woo KANG, Jong-Won KIM, Ho-Joon LEE, Kyu-Baik CHANG, Won-Young CHUNG
  • Patent number: 9235664
    Abstract: A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Rok Kim, Kyu-Baik Chang, Young Kwan Park, Seung Chul Lee, Jin Kyu Park
  • Publication number: 20100114553
    Abstract: A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.
    Type: Application
    Filed: October 28, 2009
    Publication date: May 6, 2010
    Inventors: Kyung Rok Kim, Kyu-Baik Chang, Young Kwan Park, Seung Chul Lee, Jin Kyu Park
  • Publication number: 20070087529
    Abstract: Disclosed is a simulation method for determining wafer warpage. This method includes dividing layers and evaluating a composition ratio of materials composing the layers. The method mathematically transforms a semiconductor device, which is constructed as a complicated structure with various materials, into a simplified, mathematically equivalent stacked structure comprising a plurality of unit layer, and utilizes values of mechanical characteristics, which are obtained from the transformed layer structure, for estimating wafer warpage. As a result, it is possible to complete an operation of wafer warpage simulation using information about pattern density of the semiconductor device.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 19, 2007
    Inventors: Won-Young Chung, Tai-Kyung Kim, Young-Kwan Park, Ui-Hui Kwon, Kyu-Baik Chang
  • Publication number: 20060272561
    Abstract: A deposition apparatus may include a deposition-preventing member for preventing deposition of process gas on a portion of substrate removeably arranged inside a processing chamber. The deposition-preventing member may include a fixing member for fixing the deposition preventing member to a fixed body of the processing chamber, a blocking member for blocking the to-be-blocked portion of the substrate to be processed, and a guiding member for guiding fluid and particles out from the processing chamber, the guiding member may include a guiding surface that prevents a vortex from forming on the deposition-preventing member when fluid and particles are flowing out of the processing chamber.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 7, 2006
    Inventors: Kyu-Baik Chang, Tai-Kyung Kim, Jae-Hyun Han, Won-Young Chung, Hyung-Kyu Kim