Patents by Inventor Kyu Bong KONG
Kyu Bong KONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11079787Abstract: A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.Type: GrantFiled: June 1, 2020Date of Patent: August 3, 2021Assignee: SK hynix Inc.Inventors: Kyu Bong Kong, Jae Hyeok Yang, Gang Sik Lee
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Publication number: 20210096588Abstract: A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.Type: ApplicationFiled: June 1, 2020Publication date: April 1, 2021Applicant: SK hynix Inc.Inventors: Kyu Bong KONG, Jae Hyeok YANG, Gang Sik LEE
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Patent number: 10790038Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.Type: GrantFiled: December 11, 2018Date of Patent: September 29, 2020Assignee: SK hynix Inc.Inventors: Soo Young Jang, Kyu Bong Kong, Geun Il Lee, Yong Suk Joo, Kyung Ho Chu
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Publication number: 20190385689Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.Type: ApplicationFiled: December 11, 2018Publication date: December 19, 2019Applicant: SK hynix Inc.Inventors: Soo Young JANG, Kyu Bong KONG, Geun Il LEE, Yong Suk JOO, Kyung Ho CHU
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Patent number: 10127973Abstract: A training controller, semiconductor device and a system including the same are disclosed, which relates to technology for training a phase of data. The training controller may include a read training circuit configured to control a read training operation based on a read signal and a control signal. The training controller may include a write training circuit configured to control a write training operation based on a write signal and a write training signal. The training controller may include a reset controller configured to generate a reset signal when a mismatch occurs in the read training operation or the write training operation.Type: GrantFiled: April 17, 2017Date of Patent: November 13, 2018Assignee: SK hynix Inc.Inventors: Seo Jun Kim, Kyu Bong Kong
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Publication number: 20180130516Abstract: A training controller, semiconductor device and a system including the same are disclosed, which relates to technology for training a phase of data. The training controller may include a read training circuit configured to control a read training operation based on a read signal and a control signal. The training controller may include a write training circuit configured to control a write training operation based on a write signal and a write training signal. The training controller may include a reset controller configured to generate a reset signal when a mismatch occurs in the read training operation or the write training operation.Type: ApplicationFiled: April 17, 2017Publication date: May 10, 2018Applicant: SK hynix Inc.Inventors: Seo Jun KIM, Kyu Bong KONG
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Patent number: 9660617Abstract: A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.Type: GrantFiled: March 23, 2015Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Kyu Bong Kong, Geun Il Lee
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Patent number: 9659905Abstract: A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller.Type: GrantFiled: March 25, 2015Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Kyu Bong Kong, Kwang Jin Na
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Patent number: 9431093Abstract: A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related information signal; and an input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal.Type: GrantFiled: March 10, 2015Date of Patent: August 30, 2016Assignee: SK Hynix Inc.Inventor: Kyu-Bong Kong
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Publication number: 20160180914Abstract: A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related information signal; and an input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal.Type: ApplicationFiled: March 10, 2015Publication date: June 23, 2016Inventor: Kyu-Bong KONG
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Publication number: 20160164501Abstract: A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.Type: ApplicationFiled: March 23, 2015Publication date: June 9, 2016Inventors: Kyu Bong KONG, Geun Il LEE
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Publication number: 20160147250Abstract: A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller.Type: ApplicationFiled: March 25, 2015Publication date: May 26, 2016Inventors: Kyu Bong KONG, Kwang Jin NA
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Patent number: 9281051Abstract: A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address.Type: GrantFiled: October 17, 2014Date of Patent: March 8, 2016Assignee: SK Hynix Inc.Inventors: Kyu Bong Kong, Kwang Jin Na
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Publication number: 20150380075Abstract: A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address.Type: ApplicationFiled: October 17, 2014Publication date: December 31, 2015Inventors: Kyu Bong KONG, Kwang Jin NA