Abstract: A fuse circuit may include a fuse cut detection unit to output state information indicating whether or not a fuse is cut during a fuse cut detection time period, a maintenance and output unit to maintain the state information and output a fuse state information signal, and a connection/disconnection unit to connect the fuse cut detection unit to the maintenance and output unit during the fuse cut detection time period and disconnect the fuse cut detection unit from the maintenance and output unit after the fuse cut detection time period. A fuse circuit may recognize an indefinite voltage at a detection node caused by a leakage path through a fuse as a predetermined fuse state.

Abstract: A fuse circuit may include a fuse cut detection unit to output state information indicating whether or not a fuse is cut during a fuse cut detection time period, a maintenance and output unit to maintain the state information and output a fuse state information signal, and a connection/disconnection unit to connect the fuse cut detection unit to the maintenance and output unit during the fuse cut detection time period and disconnect the fuse cut detection unit from the maintenance and output unit after the fuse cut detection time period. A fuse circuit may recognize an indefinite voltage at a detection node caused by a leakage path through a fuse as a predetermined fuse state.

Abstract: A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

Abstract: A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

Abstract: Output drivers in semiconductor memory devices such as Rambus DRAM prevent degradation of the signal characteristics of a channel bus line in a memory module equipped with the semiconductor memory devices. Each semiconductor memory device includes blocks of memory cells. The data of a memory cell in a block is transmitted to a data input/output line through an output driver for the block. The output driver includes a first transistor connected to a reference voltage (ground) and a second transistor. The first transistor is responsive to the data from the selected block. The second transistor selectively connects the first transistor to the data input/output line in response to a column cycle signal for selecting the block or a read control signal containing calibration information about the characteristics of the data input/output line. Data from the selected block is transmitted to the data input/output line via the first and second transistors when the second transistor responds to the column cycle signal.

Abstract: A chip information output circuit including a fuse box, capable of reducing a layout area without affecting input capacitance, is provided. The chip information output circuit includes a plurality of fuse blocks for generating different outputs according to whether a fuse is cut and a pipeline circuit for receiving a plurality of signals, which are output in parallel from the respective fuse blocks, and serially outputting the plurality of signals. Each of the fuse blocks includes a plurality of fuse boxes for generating output signals, the levels of which are either a high or low logic level according to whether the fuses included therein are cut, wherein the respective fuse boxes are enabled in response to the respective control signals and the output lines of the fuse boxes are wired by an OR operation. The pipeline circuit includes a plurality of serially connected latch units for latching signals output from the fuse blocks and outputting the latched signals.

Abstract: Output drivers in semiconductor memory devices such as Rambus DRAM prevent degradation of the signal characteristics of a channel bus line in a memory module equipped with the semiconductor memory devices. Each semiconductor memory device includes blocks of memory cells. The data of a memory cell in a block is transmitted to a data input/output line through an output driver for the block. The output driver includes a first transistor connected to a reference voltage (ground) and a second transistor. The first transistor is responsive to the data from the selected block. The second transistor selectively connects the first transistor to the data input/output line in response to a column cycle signal for selecting the block or a read control signal containing calibration information about the characteristics of the data input/output line. Data from the selected block is transmitted to the data input/output line via the first and second transistors when the second transistor responds to the column cycle signal.

Abstract: A semiconductor memory device having a single-cycle internal read/write function provides data relocation at high speed. Data is read from a first or source address location and then transferred directly from the sense amps to write drivers for writing to a destination address without latching in the interim. Accordingly, chip area is reduced by elimination of the I/O latch circuits. Since both the data read and write operations are performed during one cycle time, the cycle time is reduced while the bandwidth is increased. The invention has particular application to frame buffer memories and the like.

Abstract: A semiconductor memory device having an internal copy function. The memory device includes a memory cell array composed of a plurality of memory cells coupled to a plurality of bit lines, a plurality of column selectors coupled between the bit lines and an input/output data line for being turned on in response to a column select signal, a data amplifying circuit coupled to the input/output data line for amplifying the readout data, a data storage for receiving and latching the amplified data, and a write driver for outputting the latched data to the input/output data line.