Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: A non-volatile memory device includes a sensing circuit that is configured to detect a charge of a common source line and a voltage controller that is configured to vary a level of a voltage being inputted to a word line in response to a result of the detection of the sensing circuit.

Abstract: A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a voltage level of the sense node in response to a value of the program data, changing the voltage level of the sense node in response to a program state of the selected memory cell coupled to the bit line, and performing a program verification operation on the selected memory cell by sensing the voltage level of the sense node.

Abstract: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

Abstract: A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

Abstract: A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to a sensing node in accordance with a first data transmitting signal or a second data transmitting signal, and (m?1) sensing node discharging circuits configured to couple the sensing node to ground in accordance with data stored in a first node or a second node of each of the second to mth registers, and a first sensing node discharge signal or a second sensing node discharge signal.

Abstract: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

Abstract: A method of programming a nonvolatile memory device comprises storing first data of a first memory block in a page buffer unit, and then programming the first data into a redundant memory block coupled to the page buffer unit, storing second data of a second memory block in the page buffer unit, and then programming the second data into the first memory block, storing third data of a third memory block in the page buffer unit, and then programming the third data into the second memory block, storing the second data of the first memory block in the page buffer unit, and then programming the stored second data into the third memory block, and storing the first data stored in the redundant memory block in the page buffer unit, and then programming the stored first data into the first memory block.

Abstract: A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a voltage level of the sense node in response to a value of the program data, changing the voltage level of the sense node in response to a program state of the selected memory cell coupled to the bit line, and performing a program verification operation on the selected memory cell by sensing the voltage level of the sense node.

Abstract: A non-volatile memory device includes a sensing circuit that is configured to detect a charge of a common source line and a voltage controller that is configured to vary a level of a voltage being inputted to a word line in response to a result of the detection of the sensing circuit.

Abstract: A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

Abstract: In a non-volatile memory device, the level of a verifying voltage supplied to a word line is adjusted in accordance with occurrence of a source line bouncing phenomenon. The non-volatile memory device includes a bouncing sensing circuit configured to compare a source line current passing through a common source line with a reference current, and output a bouncing sensing signal in accordance with the comparing result, and a word line voltage controller configured to provide a verifying voltage increased by a certain level to a word line in accordance with level of the bouncing sensing signal.

Abstract: A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to a sensing node in accordance with a first data transmitting signal or a second data transmitting signal, and (m-1) sensing node discharging circuits configured to couple the sensing node to ground in accordance with data stored in a first node or a second node of each of the second to mth registers, and a first sensing node discharge signal or a second sensing node discharge signal.

Abstract: A non-volatile memory device for adjusting level of a verifying voltage supplied to a word line in accordance with occurrence of a source line bouncing phenomenon is disclosed. The non-volatile memory device includes a bouncing sensing circuit configured to compare a source line current passing through a common source line with a reference current, and output a bouncing sensing signal in accordance with the comparing result, and a word line voltage controller configured to provide a verifying voltage increased by a certain level to a word line in accordance with level of the bouncing sensing signal.

Abstract: A repair fuse circuit includes an address comparator, and a plurality of I/O bus select bit output units. The address comparator outputs repair signals for selecting a redundant column that will replace a full column of a plurality of redundant columns according to a column address. The plurality of I/O bus select bit output units for outputting signals corresponding to respective bits of I/O bus repair signals for selecting an I/O bus to which the redundant column will be connected according to the repair signals.

Abstract: A repair fuse circuit includes an address comparator, and a plurality of I/O bus select bit output units. The address comparator outputs repair signals for selecting a redundant column that will replace a fail column of a plurality of redundant columns according to a column address. The plurality of I/O bus select bit output units for outputting signals corresponding to respective bits of I/O bus repair signals for selecting an I/O bus to which the redundant column will be connected according to the repair signals.