Abstract: A semiconductor device for ESD protection is provided. The semiconductor device includes a plurality of transistors having a multi-fingered structure, a plurality of multilayer interconnections separated from one another, formed in proportion to the number of common drain regions of the transistors, and connected to the common drain regions of each of the transistors; a pad conductive layer formed on the multilayer interconnections; and a plurality of contact plugs for connecting interconnections of the multilayer interconnections to one another and for connecting the multilayer interconnections to the pad conductive layer so that a current flowing in the common drain regions of the transistors may pass only through the multilayer interconnections connected to the common drain regions and may flow into the pad conductive layer. Parasitic bipolar transistors of all MOSFETs having the multi-fingered structure are turned on, thereby flowing a high current during an ESD event.

Abstract: A semiconductor device for ESD protection is provided. The semiconductor device includes a plurality of transistors having a multi-fingered structure, a plurality of multilayer interconnections separated from one another, formed in proportion to the number of common drain regions of the transistors, and connected to the common drain regions of each of the transistors; a pad conductive layer formed on the multilayer interconnections; and a plurality of contact plugs for connecting interconnections of the multilayer interconnections to one another and for connecting the multilayer interconnections to the pad conductive layer so that a current flowing in the common drain regions of the transistors may pass only through the multilayer interconnections connected to the common drain regions and may flow into the pad conductive layer. Parasitic bipolar transistors of all MOSFETs having the multi-fingered structure are turned on, thereby flowing a high current during an ESD event.

Abstract: An integrated circuit device having a first type of pads with a probing portion and a bonding portion. The integrated circuit device includes a memory cell array, a logic circuit, and a plurality of the first type of pads and a plurality of a second type of pads. The second type of pads are electrically connected to the logic circuit. The first type of pads are electrically connected to the memory cell array and the logic circuit. Only the probing portion of the first type of pads is contacted by probes during testing of the memory cell array, and the bonding portion is used exclusively for attachment of a bond wire to permit connection to an external system.

Abstract: An electrostatic protection circuit in a internal circuit isolated from a substrate bias which protects the internal circuit from static electricity with regard to any of three different sources of bias voltage. An electrostatic protection circuit is constructed for each source of bias voltage so that the internal circuit is protected from static electricity flowing through bonding pads of the isolated circuit. The protective circuit comprises a plurality of NMOS or PMOS transistors for protecting input/output buffers and drivers from the static electricity flowing through the bonding pads. The respective NMOS or PMOS transistors are connected to the respective source voltage terminals and the input/output drivers.

Abstract: Disclosed is a circuit for protecting a semiconductor device from the static electricity by discharging static electricity. When a p+/n- diode of positive direction to VDD or a PMOS transistor is not usable because a voltage higher than VDD is applied, a vertical PNP transistor is connected to Vss and positive static electricity is discharged. Negative static electricity is discharged by using an n+/p- diode connected to Vss direction through a semiconductor substrate. Additionally, in case of a circuit to which either a voltage higher than VDD, or a voltage lower than Vss (=0?V!) is inputted, or outputted, a discharging path is formed with respect to negative static electricity by the operation of a vertical NPN bipolar junction transistor connected to VDD. Positive static electricity is discharged via a p+/n- diode connected to VDD.