Patents by Inventor Kyu-Hyung YOON

Kyu-Hyung YOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250085244
    Abstract: The technology disclosed in the present specification is a method of evaluating insulation performance of a low-temperature storage tank, the method including an operation of transferring an internal electrode to a lower base material, wherein the operation includes: a first operation of measuring an amount of infrared energy of a sensor pad; a second operation of assuming a temperature of a substrate of the sensor pad as a specific value; a third operation of calculating a temperature of a first surface of the sensor pad by using the amount of the infrared energy measured from the sensor pad and the temperature of the substrate; a fourth operation of obtaining a temperature of the substrate from a transient heat conduction equation by using the temperature of the first surface as a boundary condition; a fifth operation of determining whether the obtained temperature of the substrate is equal to the assumed temperature of the substrate; and a sixth operation of, when the temperatures of the substrate are equa
    Type: Application
    Filed: November 26, 2021
    Publication date: March 13, 2025
    Inventors: Tae Hoon KIM, Kyu Hyung DO, Byung Il CHOI, Yong Shik HAN, Ae Jung YOON, Hwa Long YOU
  • Patent number: 9484335
    Abstract: A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 1, 2016
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim, Ju-Hyun Myung, Kyu-Hyung Yoon
  • Patent number: 8906775
    Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Tae-Yoon Kim, Kyu-Hyung Yoon
  • Publication number: 20140097519
    Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.
    Type: Application
    Filed: December 17, 2012
    Publication date: April 10, 2014
    Applicant: SK HYNIX INC.
    Inventors: Heung-Jae CHO, Eui-Seong HWANG, Tae-Yoon KIM, Kyu-Hyung YOON
  • Publication number: 20140061850
    Abstract: A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventors: Heung-Jae CHO, Eui-Seong HWANG, Eun-Shil PARK, Tae-Yoon KIM, Ju-Hyun MYUNG, Kyu-Hyung YOON