Patents by Inventor Kyu-II Yeon

Kyu-II Yeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9831543
    Abstract: An adaptable antenna apparatus for a base station is provided. The adaptable antenna apparatus includes a first antenna having a first antenna array, a second antenna rotatably coupled to the first antenna and having a second antenna array, and a main controller provided in one of the first antenna and the second antenna, wherein the main controller is configured to apply a control signal to the first antenna and the second antenna.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hyeon Choi, Han-Seok Kim, Kyu-II Yeon, Byung-Tae Yoon, Jun-Sung Lee, Nam-Ryul Jeon
  • Patent number: 9565617
    Abstract: A method and apparatus for configuring a routing path in a wireless communication system are provided. The method includes measuring a first distance between the terminal and a target terminal, transmitting information of the measured first distance to at least one neighboring terminal, receiving a second distance measured for the target terminal with respect to the terminal from the at least one neighboring terminal, and determining a neighboring terminal of which the second distance is the longest as a next terminal of the routing path.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hyeon Choi, Kyu-II Yeon, Han-Seok Kim, Jun-Sung Lee
  • Publication number: 20080148087
    Abstract: An apparatus and method of time keeping for a non-real-time OS is provided. The apparatus includes a processor and a Field Programmable Gate Array (FPGA). The processor requests performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a DPRAM R/W time interval in a Time Division Multiple Access (TDMA) scheme using a system clock. Upon receipt of the DPRAM R/W operation performance request from the processor, the FPGA compares the operation performance request time with an access time table defining a DPRAM R/W time interval for each processor, generated in the TDMA scheme using the system clock. The FPGA performs the operation requested by the processor when the operation performance request has been made in the DPRAM R/W time interval of the processor.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 19, 2008
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Keun-Bok KIM, Kyu-II Yeon