Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A sterilization module including a light source configured to irradiate ultraviolet light, a board on which the light source is mounted, a protective tube accommodating the board therein and configured to transmit ultraviolet light irradiated from the light source, a first base coupled to one side of the protective tube, and a second base coupled to the other side of the protective tube, in which at least one of the first base and the second base includes an insertion part to be inserted into the protective tube, the insertion part having a first diameter when viewed in a first cross-section perpendicular to a length direction of the protective tube, and a cover part integrally formed on the insertion part and having a second diameter greater than the first diameter in the first cross-section.

Abstract: A method of and an electronic device for performing a power-saving mode in the electronic device, according is provided. The method includes driving at least one processor; detecting a command for switching to a power-saving mode; and if the command for switching to the power saving mode is detected, limiting operations of the at least one processor to block set functions other than a power saving call function in accordance with at least one set power saving scheme.

Abstract: A multi-chip package is provided. The multi-chip package may include a frame interposer, a first chip stack with n number of semiconductor chips on a first surface of the frame interposer, and a second chip stack with m number of semiconductor chips on a second surface of the frame interposer. The interposer may have first and second openings. The first chip stack may extend over one of the first and second openings and may expose the other of the first and second openings. The second chip stack may extend over the other of the first and second openings and may expose the one of the first and second openings.

Abstract: A multi-chip package is provided. The multi-chip package may include a frame interposer, a first chip stack with n number of semiconductor chips on a first surface of the frame interposer, and a second chip stack with m number of semiconductor chips on a second surface of the frame interposer. The interposer may have first and second openings. The first chip stack may extend over one of the first and second openings and may expose the other of the first and second openings. The second chip stack may extend over the other of the first and second openings and may expose the one of the first and second openings.

Abstract: A semiconductor package may include a semiconductor chip assembly, a signal input/output member and an encapsulating member. The semiconductor chip assembly may include first pads and second pads. The first pads may be exposed in a first direction. The second pads may be exposed in a second direction substantially opposite to the first direction. The signal input/output member may include first terminals and second terminals. The first terminals may be electrically connected to the first pads. The second terminals may be electrically connected to the second pads. The encapsulating member may encapsulate the semiconductor chip assembly.