Abstract: Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal.

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract: A semiconductor structure according to some examples may include an LC component for use in PMIC applications. The semiconductor structure may have a first conductive coil mounted on an upper surface of a substrate, the first conductive coil surrounding a magnetic core; an output located on a surface of the first conductive coil and coupled to the coil; a dielectric layer located on a surface of the output; and an upper conductive element located on a surface of the dielectric layer, wherein the upper conductive element, the dielectric layer, and the output form a capacitor; and the first conductive coil and the magnetic core form an inductor. The semiconductor structure may also include a second conductive coil located in a same horizontal plane as the first conductive coil, the second conductive coil surrounding a magnetic core where the first conductive coil and the second conductive coil form a fishbone pattern.

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Abstract: A method of additive tuning a resistor includes measuring resistance across a recessed area of the resistor using at least two terminals, depositing resistance material from an ink jet across the recessed area of the resistor device concurrently with the measuring resistance, and ceasing the depositing upon obtaining a measurement of a resistance threshold value.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract: A ceramic capacitor is provided that includes a first capacitor surface, a second opposing capacitor surface, and metal plates perpendicular to the first capacitor surface and second opposing capacitor surface. The metal plates extend from the first capacitor surface to the second opposing capacitor surface. The ceramic capacitor is capable of being interposed between a die and a substrate. A portion of the metal plates are capable of being coupled to conductive pads of the die on the first capacitor surface and to conductive pads of the substrate on the second capacitor surface.

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract: Systems and methods for EMC, EMI and ESD testing are described. A probe comprises a center conductor extending along an axis of the probe, a probe tip, and a shield coaxially aligned with the center conductor and configured to provide electromagnetic screening for the probe tip. One or more actuators may change the relative positions of the probe tip and shield with respect to a device under test, thereby enabling control of sensitivity and resolution of the probe.

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract: A high-speed, high-density Input/Output bridge couples dies on a substrate to each other using a flexible connector that is attached to the substrate using solder balls disposed in openings in the substrate. Thus, the bulky, male-to-female connectors and/or silicon bridges are eliminated while still permitting dies disposed on the substrate to be coupled together.

Abstract: An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer.

Abstract: Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract: Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.