Abstract: A display controller includes a frame rate converter creating a second reference image having a second frame rate higher than a first frame rate of a first reference image, based on the first reference image, a buffer storing the second reference image, and an image processor creating an output image by selecting at least a portion of the second reference image.

Abstract: A display controller includes a frame rate converter creating a second reference image having a second frame rate higher than a first frame rate of a first reference image, based on the first reference image, a buffer storing the second reference image, and an image processor creating an output image a user by selecting at least a portion of the second reference image.

Abstract: An OP-amplifier with an offset cancellation circuit is provided. The OP-amplifier includes: an input unit having a mirror circuit and first and second differential input circuits, the mirror circuit having first and second output terminals, the first differential input circuit having a first bias circuit and the second differential input circuit having a second bias circuit; an output unit for amplifying output signals of the first and second differential input circuits; and a differential mode feedback circuit for sensing a voltage difference between an output voltage and an input voltage applied to the first and the second differential input circuits, for outputting a first voltage and a second voltage based on the voltage difference, and for feeding back the first voltage to the first bias circuit and feeding back the second voltage to the second bias circuit to remove an offset voltage.

Abstract: An OP-amplifier with an offset cancellation circuit is provided. The OP-amplifier includes: an input unit having a mirror circuit and first and second differential input circuits, the mirror circuit having first and second output terminals, the first differential input circuit having a first bias circuit and the second differential input circuit having a second bias circuit; an output unit for amplifying output signals of the first and second differential input circuits; and a differential mode feedback circuit for sensing a voltage difference between an output voltage and an input voltage applied to the first and the second differential input circuits, for outputting a first voltage and a second voltage based on the voltage difference, and for feeding back the first voltage to the first bias circuit and feeding back the second voltage to the second bias circuit to remove an offset voltage.

Abstract: A planar antenna is provided. The planar antenna includes a conductor plate for radiating radio waves to free space, an upper dielectric layer attached to the upper side of the conductor plate, a feeder unit attached to the upper surface of the upper dielectric layer for feeding current for the wave radiation of the conductor plate, and a plurality of dielectric layers attached to the lower side of the conductor plate and including at least one air layer. The planar antenna having the ring-slot radiation device according to the present invention has a very simple structure and occupies a small space since it has a planar structure and uses only one radiation device. It is possible to increase the efficiency and the gain of the antenna by using the multiple layer dielectric in which the air layer is inserted between the dielectric layers of the planar antenna. The planar antenna can be easily manufactured even in the millimetric-wave bandwidth.

Abstract: A method for transferring DMA data between the video port and the host interface in a multimedia processor is disclosed. The method includes determining whether one frame data should be transferred between the host interface and the video port; preloading some DMA instructions in the frame buffer and setting the DMA register to be fitted for the DMA operation; and fetching the preloaded instructions from the frame buffer subsequently by the DMA controller to perform video data transfer at a predetermined data bandwidth. According to this invention, the time consumption of a microprocessor for programming the DMA controller is reduced, thereby enhancing the data transfer rate between the host interface and video port of the multimedia computer system.

Abstract: Transmit adaptive phased array antenna system and receive adaptive phased array antenna system are disclosed which include a transmitter unit; a power divider unit which is connected to the transmitter unit, and when transmitting, divides computed weights; a receiver unit; an array antenna unit wherein multiple basic elements of antenna are spatially arrayed; a power feeder unit which, at the time of receiving, receives receive signal of the array antenna unit and changes amplitude and phase of the receive signal according to another control signal, and at the time of transmitting, receives divided signal from the power divider unit; a power combiner unit which sums receive signals, which are received from the power feeder unit, by using weights; an amplitude detector unit which checks the amplitude of the signals which are received from the power combiner unit, and transmits them to the receiver unit; a beam control unit which receives a portion of the amplitude of summed signals from the amplitude detector,