Abstract: An organic light-emitting display apparatus including first and second edge sub-pixel lines disposed at opposing side edges of the apparatus and center sub-pixel lines disposed therebetween, each for emitting a single color of light. An external emission width of the first edge sub-pixel line is less than an external emission width of the center sub-pixel lines that emit the same color. An external emission width of the second edge sub-pixel line is less than the width of the center sub-pixel lines that emit the same color.

Abstract: A wall mount is disclosed. The wall mount can include a bracket and a frame, where the frame can be configured to support an outward portion of the bracket. The frame can be open to one side, and a guide part can be formed on the frame to guide the bracket in such a way that the bracket may be slidably inserted into the frame from the one side of the frame. In certain embodiments of the invention, the adjusting screws can be utilized to enable levelness adjustment, so that the wall mount can be installed in a more convenient manner, and the levelness of the bracket can be adjusted easily and accurately.

Abstract: A tilting device is disclosed. The tilting device may include: an arm, on which a tilt-shaft is formed; a tilt-base coupled to the tilt-shaft in a manner that allows tilting; a pulley rotatably coupled to the tilt-base; a wire, which is wound around the pulley, and of which either end is coupled to either side of the arm on opposite sides of the tilt-shaft; and a driving unit, which drives the pulley. An embodiment of the invention enables tilting operations using a smaller driving device, and also allows manual operations.

Abstract: Disclosed herein are a method for plating a printed circuit board and the printed circuit board manufactured therefrom. In the method, a bare soldering or wire bonding portion of a copper (Cu)- or copper alloy layer, is plated with palladium (Pd) or a palladium alloy, and then gold (Au) or a gold alloy is deposited over the palladium or palladium alloy plated layer by an electroless substitution plating process based on ionization tendency. Having superior hardness, ductility and corrosion resistance, palladium is suitable for use between a connector and a substrate and meets requirements for the printed circuit board even when applied to a low thickness, greatly reducing the process time. Accordingly, the problem of black pad, which frequently occur on electroless nickel and electroless gold finish upon surface mount technology, can be perfectly solved. Particularly, fatal bending cracks can be prevented from occurring in the rigid-flexible or flexible printed circuit boards.

Abstract: An inspecting apparatus for semiconductor devices including: a match plate; a contact module combined with the match plate, and the match plate including a radiation unit radiating heat from the semiconductor devices to the outside, and a test unit contacting leads of the semiconductor; an insert module installed on a bottom of the contact module, and having a semiconductor device accommodator to accommodate the semiconductor device; and an auxiliary radiation member installed on a bottom of the insert module, and radiating the heat from the semiconductor device to the outside. Accordingly, the inspecting apparatus for semiconductor device according to the present invention performs testing at a constant temperature regardless of heat from the semiconductors by radiating the heat from the semiconductors immediately and efficiently, thereby producing more accurate test results.

Abstract: The present invention is related to a method of fabricating a rigid-flexible printed circuit board. Specifically, this invention relates to a method of fabricating a rigid-flexible printed circuit board, in which an internal circuit pattern exposed for use in an external pad and a mounting pad is protected from external environments using a resist cover by window etching the base copper foil of a flexible region upon formation of an external circuit pattern as opposed to using a resist cover. Thus the number of fabrication processes and the fabrication costs are decreased and the increase in defect rates due to contamination is prevented, resulting in maximized reliability.

Abstract: A semiconductor device test apparatus includes a main body and a stacker for stacking devices before and after a test. The stacker includes at least one user tray feeder predesignated with a function for stacking un-tested devices and at least one user tray sender predesignated with a function for stacking tested devices, the user tray functions being interchangeable during stacker operation.

Abstract: An inspecting apparatus for semiconductor devices including: a match plate; a contact module combined with the match plate, and the match plate including a radiation unit radiating heat from the semiconductor devices to the outside, and a test unit contacting leads of the semiconductor; an insert module installed on a bottom of the contact module, and having a semiconductor device accommodator to accommodate the semiconductor device; and an auxiliary radiation member installed on a bottom of the insert module, and radiating the heat from the semiconductor device to the outside. Accordingly, the inspecting apparatus for semiconductor device according to the present invention performs testing at a constant temperature regardless of heat from the semiconductors by radiating the heat from the semiconductors immediately and efficiently, thereby producing more accurate test results.

Abstract: A memory string for using in an EEPROM device is provided which has two selection transistors and a plurality of depletion-type floating gate transistors whose drain-source paths are connected in series with each other between two selection transistors.

Abstract: An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.

Abstract: An electrically page erasable and programmable read only memory device is an EEPROM device which is erasable page by page, and consists of flash-type floating gate transistors as the memory cells. The memory cell array of the device is divided by a plurality of pages, wherein each page comprises a plurality of bit lines, a plurality of common source lines, and a plurality of word lines. A plurality of erase selection circuits are arranged and correspond to the respective pages in order to erase the cells in a selected page, wherein each erase selection circuit comprises a passing transistor, a gate, a voltage stabilizing transistor, and an erasing line.

Abstract: There is disclosed a programmable sequential code recognition circuit comprising an individual code recognition circuit for recognizing each input code, and a sequence recognition circuit for recognizing the sequency given for individual codes obtained by combination of input signals, so that a specific mode may be selected by the input combination sequentially inputted.

Abstract: A data output buffer being capable of precharging a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in a semiconductor chip. The buffer includes means for minimizing the DC current consumption of a data bus precharge driver by feeding back an electric potential of an I/O port to an input of the precharging driver, and means for making the precharge driver operate during a specified period of time prior to providing the actual data by using an ATD pulse.

Abstract: An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the flo