Patents by Inventor Kyu-yong Kim

Kyu-yong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200164442
    Abstract: The present invention relates to a low-temperature sinterable copper particle material prepared using an electride and an organic copper compound and a preparation method therefor and, more particularly, to a copper nanoparticle which can be useful as a conductive copper ink material thanks to its small size and high dispersibility, and a method for preparing the copper nanoparticle by reducing an organic copper compound with an electride as a reducing agent. The present invention provides copper nanoparticles which can be suitably used as a conductive copper nanoink material because the copper nanoparticles show the restrained oxidation of the copper, have an average particle diameter of around 5 nm to cause the depression of melting point, are of high dispersibility, and allow the removal of the electride in a simple ultrasonication process.
    Type: Application
    Filed: March 7, 2018
    Publication date: May 28, 2020
    Applicant: Research & Business Foundation Sungkyunkwan University
    Inventors: Sung-wng KIM, Kyu-hyoung LEE, Ye-ji KIM, Jong-ho PARK, Seung-yong LEE
  • Publication number: 20200149583
    Abstract: The present invention provides a vehicle air compressor including a shaft provided with an impeller disposed at one side thereof and a runner disposed at the other side thereof, a motor configured to rotate the shaft, a trust bearing which supports the shaft in a longitudinal direction of the shaft and of which a surface is disposed adjacent to a surface of the runner, wherein a cooling hole for cooling air between the trust bearing and the runner is disposed in the trust bearing.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 14, 2020
    Inventors: Jong Sung LEE, Hyun Chil KIM, Gun Woong PARK, Chi Yong PARK, Hyun Sup YANG, Kyu Sung CHOI
  • Publication number: 20200140832
    Abstract: The present invention relates to a peptide with anti-inflammatory activity, wherein the peptide comprises any one amino acid sequence of SEQ ID NO:1 to SEQ ID NO:161, the peptide has above 80% homology of amino acid sequence with above-mentioned sequences, or the peptide is the fragment of the above-mentioned peptides. The present invention also relates to an inflammatory composition comprising the above mentioned peptides. According to the present invention, a peptide that has at least one amino acid sequence of SEQ ID NO:1 to SEQ ID NO:161 has outstanding efficacy in both suppressing inflammation and in prophylactic means. Therefore, the composition comprising the peptides of this invention can be used as anti-inflammatory pharmaceutical compositions or as cosmetic compositions, in turn, treating and preventing a variety of different types of inflammatory diseases.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 7, 2020
    Inventors: Sang Jae KIM, Kyung Hee KIM, Kyu-Yong LEE, Seong-Ho KOH, Bum Joon KIM, Hyun-Hee PARK, Sung Jin HUH, Woo Jin LEE, Hwain JANG, Jung Soon HA
  • Patent number: 10643994
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Patent number: 10625883
    Abstract: The invention is an auto-packing apparatus for pouch, and comprises: a pouch conveyor 20, a slot magazine 50, a pickup means 60 to pick up the moving pouches 1 on the pouch conveyor 20 and insert them into the slots 51 of the slot magazine 50, a pouch retainer 100 to retain the pouches 1 dropping from the slot magazine 50, a moving means 130 to move one 80 of the side walls 70,80 of the pouch retainer 100 and an opening means 91 to open and close the lower part of the pouch retainer 100 and a controller 180.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 21, 2020
    Assignees: YUHANNCI CO., LTD., AESTURA CORPORATION
    Inventors: Seok tae Kim, Jae in Kim, Sung woo Lee, Jong myung Park, Kyu yong Park
  • Publication number: 20200072874
    Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.
    Type: Application
    Filed: January 29, 2019
    Publication date: March 5, 2020
    Inventors: YOUNG DO KIM, SUNG YONG LIM, CHAN SOO KANG, DO HOON KWON, MIN JU KIM, SANG KI NAM, JUNG MO YANG, JONG HUN PI, KYU HEE HAN
  • Publication number: 20200005994
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Kyu-Oh LEE, Rahul JAIN, Sai VADLAMANI, Cheng XU, Ji Yong PARK, Junnan ZHAO, Seo Young KIM
  • Publication number: 20190393217
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Application
    Filed: May 3, 2019
    Publication date: December 26, 2019
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20190394359
    Abstract: An image sensor is provided. The image sensor may include an active pixel electrically connected to a column line and configured to provide an output voltage to a pixel node and a bias circuit electrically connected between the pixel node and an earth terminal, and in which a first current flows through a first line electrically connected to the pixel node, wherein the bias circuit includes a first variable capacitor electrically connected to a power supply voltage, and a second variable capacitor electrically connected to the earth terminal, and the magnitude of the first current may be configured to vary based on a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor. The output voltage may be configured to be adjusted based on the magnitude of the first current.
    Type: Application
    Filed: September 4, 2019
    Publication date: December 26, 2019
    Inventors: Kyu Ik Cho, Ji Yong Kim, Jae Jung Park
  • Publication number: 20190355675
    Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Kyu-Oh LEE, Sai VADLAMANI, Rahul JAIN, Junnan ZHAO, Ji Yong PARK, Cheng XU, Seo Young KIM
  • Patent number: 10456796
    Abstract: Disclosed herein are a spray nozzle for an attemperator and an attemperator including the spray nozzle. An attemperator according to an embodiment includes: a steam transfer pipe through which steam is transferred; a fixed pipe which is fixed to an outer surface of the steam transfer pipe; and a spray nozzle, which is coupled to the fixed pipe, disposed in the steam transfer pipe and configured to spray cooling water into the steam transfer pipe. The spray nozzle includes, on an outer circumferential surface thereof, at least one support that protrudes toward the fixed pipe. The spray nozzle is spaced apart from the fixed pipe.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: October 29, 2019
    Assignee: Doosan Heavy Industries Construction Co., Ltd.
    Inventors: Dong Wook Kim, Kyu Man Kim, Woo Seong Song, Jae Cheol Kim, Cheol Hong Kim, Tae Jun Yun, Seong Yong Jeong
  • Patent number: 10450507
    Abstract: A quantum dot includes a seed and a core enclosing the seed. The core is grown from the seed to improve size uniformity of the core. The seed includes a first compound without Cd. The first compound may be GaP. The core may include a second compound including elements from group XIII and group XV. The second compound may be InP. The quantum dot may also include a first shell of a third compound enclosing the core. The third compound may be ZnSe or ZnS. The quantum dot may also include a second shell of a fourth compound enclosing the first shell. The fourth compound may be ZnS when the third compound is ZnSe. Embodiments also relate to a quantum dot including first to third elements selected from XIII group elements and XV group elements and fourth to sixth elements selected from XII group elements and XVI group elements.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 22, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Kyung-Kook Jang, Byung-Geol Kim, Wy-Yong Kim, Kyu-Nam Kim, Hee-Yeol Kim, Sung-Il Woo, Do-Hyung Kim, Tae-Yang Lee
  • Patent number: 10447898
    Abstract: An image sensor is provided. The image sensor may include an active pixel electrically connected to a column line and configured to provide an output voltage to a pixel node and a bias circuit electrically connected between the pixel node and an earth terminal, and in which a first current flows through a first line electrically connected to the pixel node, wherein the bias circuit includes a first variable capacitor electrically connected to a power supply voltage, and a second variable capacitor electrically connected to the earth terminal, and the magnitude of the first current may be configured to vary based on a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor. The output voltage may be configured to be adjusted based on the magnitude of the first current.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu Ik Cho, Ji Yong Kim, Jae Jung Park
  • Publication number: 20190304661
    Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • Publication number: 20190304933
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng XU, Kyu-Oh LEE, Junnan ZHAO, Rahul JAIN, Ji Yong PARK, Sai VADLAMANI, Seo Young KIM
  • Publication number: 20190273299
    Abstract: Disclosed is a low-pass filter connected to a capacitor by a T-junction and used for a multiplexer. The low-pass filter includes: a plurality of capacitor elements which is formed of a capacitive conductor of a disk shape; and a plurality of inductor elements which connects the capacitor elements to each other and is formed in a rod shape. The plurality of capacitor elements and the plurality of inductor elements are alternately arranged, and the capacitor element which is connected to the capacitor has a capacitance value smaller than a capacitance value which is determined by a cut-off frequency of the low-pass filter.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventor: Kyu Yong KIM
  • Patent number: 10373951
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20190237861
    Abstract: A chip antenna includes a radiation portion having a block shape and a first surface and a second surface opposing each other, and configured to receive and radiate a feed signal as an electromagnetic wave; a first block made of a dielectric material and coupled to the first surface of the radiation portion; a second block made of a dielectric material and coupled to the second surface of the radiation portion; a ground portion having a block shape and coupled to the first block, and configured to reflect the electromagnetic wave radiated by the radiation portion back toward the radiation portion; and a director having a block shape and coupled to the second block, wherein an overall width of the ground portion, the first block, and the radiation portion is 2 mm or less, and the first block has a dielectric constant of 3.5 or more to 25 or less.
    Type: Application
    Filed: November 9, 2018
    Publication date: August 1, 2019
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Yeong KIM, Sung Yong AN, Sang Jong LEE, Seong Hee CHOI, Kyu Bum HAN, Jeong Ki RYOO, Byeong Cheol MOON, Chang Hak CHOI
  • Patent number: 10364391
    Abstract: A quantum dot includes a seed and a core enclosing the seed. The core is grown from the seed to improve size uniformity of the core. The seed includes a first compound without Cd. The first compound may be GaP. The core may include a second compound including elements from group XIII and group XV. The second compound may be InP. The quantum dot may also include a first shell of a third compound enclosing the core. The third compound may be ZnSe or ZnS. The quantum dot may also include a second shell of a fourth compound enclosing the first shell. The fourth compound may be ZnS when the third compound is ZnSe. Embodiments also relate to a quantum dot including first to third elements selected from XIII group elements and XV group elements and fourth to sixth elements selected from XII group elements and XVI group elements.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: July 30, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Kyung-Kook Jang, Byung-Geol Kim, Wy-Yong Kim, Kyu-Nam Kim, Hee-Yeol Kim, Sung-Il Woo, Do-Hyung Kim, Tae-Yang Lee
  • Publication number: 20190206822
    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Ji Yong PARK, Kyu Oh LEE, Cheng XU, Seo Young KIM