Patents by Inventor Kyu-Man HWANG
Kyu-Man HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096879Abstract: A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.Type: ApplicationFiled: April 11, 2023Publication date: March 21, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu Man HWANG, Sung Il PARK, Jin Chan YUN, Dong Kyu LEE
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Publication number: 20230326971Abstract: A semiconductor device including a lower pattern extending in a first direction, a gate electrode on the lower pattern and extending in a second direction, a lower channel pattern on the lower pattern and comprising at least one lower sheet pattern, an upper channel pattern on the lower channel pattern and comprising at least one upper sheet pattern, wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction, the gate electrode comprises a lower gate electrode through which the lower sheet pattern passes and an upper gate electrode through which the upper sheet pattern passes, the lower gate electrode comprises a lower conductive liner layer defining a trench and a lower filling layer filling the trench, and an entire bottom surface of the upper gate electrode is higher than an upper surface of the lower gate electrode, may be provided.Type: ApplicationFiled: January 3, 2023Publication date: October 12, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu Man HWANG, Sung ll Park, Jae Hyun Park, Do Young Choi
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Patent number: 10164173Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: GrantFiled: July 25, 2017Date of Patent: December 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Shi-Jung Kim, Mi-Lim Park, Jun-Soo Bae, Seung-Woo Lee
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Publication number: 20170324031Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: ApplicationFiled: July 25, 2017Publication date: November 9, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu-Man HWANG, Shi-Jung KIM, Mi-Lim PARK, Jun-Soo BAE, Seung-Woo LEE
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Patent number: 9761792Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: GrantFiled: October 20, 2015Date of Patent: September 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Shi-Jung Kim, Mi-Lim Park, Jun-Soo Bae, Seung-Woo Lee
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Patent number: 9660186Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.Type: GrantFiled: June 7, 2016Date of Patent: May 23, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jinhye Bae, Wonjun Lee, Yoonsung Han, Hoon Han, Kyu-Man Hwang, Yongsun Ko
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Publication number: 20170104152Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.Type: ApplicationFiled: June 7, 2016Publication date: April 13, 2017Inventors: Jinhye BAE, Wonjun LEE, Yoonsung HAN, Hoon HAN, Kyu-Man HWANG, Yongsun KO
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Publication number: 20160155934Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: ApplicationFiled: October 20, 2015Publication date: June 2, 2016Inventors: Kyu-Man HWANG, Shi-Jung KIM, Mi-Lim PARK, Jun-Soo BAE, Seung-Woo LEE
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Patent number: 8772121Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.Type: GrantFiled: April 10, 2012Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Jun-Soo Bae, Sung-Un Kwon, Kwang-Ho Park
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Publication number: 20120273741Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.Type: ApplicationFiled: April 10, 2012Publication date: November 1, 2012Inventors: Kyu-Man HWANG, Jun-Soo BAE, Sung-Un KWON, Kwang-Ho PARK
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Publication number: 20110220858Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device may include a lower electrode having a hollow cylindrical shape of which an upper portion is open, the lower electrode being disposed on a substrate, an insulating structure wrapping the lower electrode and including a nitride, a variable resistance pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the variable resistance pattern.Type: ApplicationFiled: March 11, 2011Publication date: September 15, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu-Man HWANG, Junsoo Bae, Hwang-Ho Park