Abstract: In one example, a device includes a redistribution layer (RDL) substrate comprising a first side and a second side opposite the first side. A wafer component can be coupled to the first side of the RDL substrate. A first bond interface can be disposed between the wafer component and the RDL substrate. The first bond interface can be provided by a first hybrid bond. An electronic component can be coupled to the second side of the RDL substrate. A second bond interface can be disposed between the electronic component and the RDL substrate. The second bond interface can be within a footprint of the first bond interface and can be provided by a second hybrid bond. A vertical interconnect can be disposed lateral to a sidewall of the electronic component. The vertical interconnect can be coupled to the RDL substrate. Other examples and related methods are also disclosed herein.

Abstract: A method of manufacturing an electronic device may include providing alignment conductive pads and internal interconnects along an upper side of a first carrier and coupling alignment interconnects of a connect component to the alignment conductive pads. The method also includes encapsulating the connect component and the internal interconnects in a lower encapsulant, and covering an upper side of the lower encapsulant with an upper substrate. The method also includes coupling, via the upper substrate, first interconnects of a first electronic component and a second electronic component to the connect component interconnects and second interconnects of the first electronic component and the second electronic component to the internal interconnects. The method further includes removing the first carrier from a lower side of the lower encapsulant, and covering the lower side of the lower encapsulant with a lower substrate. Other examples and related electronic devices are also disclosed herein.

Abstract: An example method of manufacturing an electronic device can include providing a device wafer including an active region comprising a front-end-of-line (FEOL) region opposite a back-end-of-line (BEOL) region. The FEOL region can include buried power rails, and the BEOL region can include a dielectric structure having a side exposed from the BEOL region. A support substrate having a substrate dielectric can be coupled to the dielectric structure. A bond interface is disposed between the substrate dielectric and the dielectric structure. A passivation structure can be provided over the FEOL region. Conductive vias can be provided through the passivation structure. The conductive vias can include a conductor coupled to the buried power rails. A substrate can be coupled to the passivation structure. The substrate can include a power network electrically coupled to the conductive vias.

Abstract: In one example, an electronic device can include an active region comprising a channel region. A first isolation region may be disposed at a lateral side of the channel region. A source region may be located in a footprint of the channel region and disposed between the channel region and the first isolation region. A device passivation can cover a side of the channel region opposite the source region and disposed on a lateral side of the first isolation region. A substrate passivation can be coupled to the device passivation. A bond interface can be disposed between the device passivation and the substrate passivation. A substrate can be coupled to the substrate passivation. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device includes a lower redistribution structure, an upper redistribution structure, a first electronic component coupled to the upper redistribution structure, a second electronic component coupled to the upper redistribution structure, and a routing component. The routing component includes a routing redistribution structure, a component die, component through-interconnects, and a component encapsulant. The routing redistribution structure is on the component encapsulant and coupled to the upper redistribution structure. The component die includes a component die substrate and a die interface structure on the component die substrate. The die interface structure is coupled to the routing redistribution structure. The component through-interconnects extend through the component encapsulant and couple the routing redistribution structure to the lower redistribution structure. Other examples and related methods are also disclosed herein.

Abstract: Provided is a display panel that includes: a display module that includes a liquid crystal layer, a backlight module having a light source, a light guide plate that guides light emitted from the light source to the display module, and a bottom chassis that houses the light source and the light guide plate; and a force-touch module located between the display module and the bottom chassis. The present disclosure makes force-touch sensing possible even under the presence of an air gap inside the display panel.

Abstract: The touch panel comprises: a first transparent substrate divided into an active area and a non-active area located around the active area; a sensing pattern part that includes first sensing cells arranged in the active area of the transparent substrate in the longitudinal direction, a second transparent substrate provided on the first sensing cells, and second sensing cells arranged on the second transparent substrate in the lateral direction; and first sensing lines and second sensing lines provided in the non-active area of the first transparent substrate to connect the first sensing cells and the second sensing cells to an external driving circuit, respectively, wherein an extended transparent substrate extending from the second transparent substrate along the interconnection wires of the second sensing cells is formed in the non-active area of the first transparent substrate.