Abstract: An on-chip temperature sensor for a semiconductor device. A temperature sensing mechanism includes a first current generator producing a first current that is proportional to absolute temperature of the semiconductor device. A second current generator produces a second current that is inversely proportional to absolute temperature of the semiconductor device. A current mode amplifier is coupled to amplifying the difference between the first current and the second current to produce a temperature signal.

Abstract: A method for controlling a memory cell capable of extending a refresh interval and lengthening a storing time of a cell data by raising a data of a high level voltage stored in the cell capacitor above Vdd, thereby reducing power consumption.

Abstract: An address transition detection circuit includes an address input unit; a first latch unit for latching an input address signal and activating an address transition detection signal; a second latch unit for latching an input level of the first latch unit at a first value in accordance with an output from the first latch unit while the address transition detection signal ATD is active; first and second delay units for delaying an output from the first latch unit; and a CMOS flip-flop for outputting the address transition detection signal having a predetermined width in accordance with outputs from the first latch unit and the first and second delay units.

Abstract: An improved address transition detection circuit prevents malfunctions of a memory by generating an address transition detection signal having a certain pulse width regardless of the width of a pulse of an address signal inputted to a memory. The circuit includes a NOR-gate for NORing an address signal and a chip selection signal, which are externally applied thereto. A level maintaining unit maintains a level of a signal outputted from the NOR-gate for a predetermined time, in accordance with first and second latch signals and first and second delay signals, to output first and second level maintaining signals of different levels. A latch latches the first and second level maintaining signals outputted from the level maintaining unit and outputs first and second latch signals. First and second signal delay units delay first and second latch signals outputted from the latch for a predetermined time and output first and second delay signals.

Abstract: An address transition detection circuit for driving an internal circuit of a memory device, includes an address input circuit for generating an input logic operation signal by a logic operation of a chip select signal and an address signal, a latch circuit for generating first and second latch signals, a feedback circuit for generating a feedback signal, first and second delay circuits for generating first and second delay signals by delaying the first and second latch signals for a prescribed delay time, and an address transition detection signal output circuit for receiving the first and second latch signals and the first and second delay signals, and generating an address transition detection signal having a pulse width longer than at least the twice the prescribed delay time of the first or second delay circuit when the address signal changes, thereby preventing malfunction of the memory device.