Abstract: A semiconductor device including channels spaced apart from each other on a substrate; a gate structure extending on the substrate, the gate structure surrounding lower and upper surfaces and sidewalls of each of the channels; and a source/drain layer on the substrate, the source/drain layer contacting sidewalls of the channels and containing silicon-germanium, the source/drain layer including: a second epitaxial layer having a second germanium concentration; and a first epitaxial layer having a first germanium concentration smaller than the second germanium concentration, the first epitaxial layer covering a lower surface and sidewalls of the second epitaxial layer, wherein the first epitaxial layer includes a protruding portion that protrudes in the first direction and contacts the gate structure, and wherein the protruding portion has a facet that is not curved.

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate, a pair of nanosheets on the fin-type active region, a gate line surrounding the pair of nanosheets, the gate line including a sub-gate portion between the pair of nanosheets, a source/drain region contacting the pair of nanosheets, and a gate dielectric film between the gate line and the pair of nanosheets and between the gate line and the source/drain region, wherein the source/drain region includes a first blocking layer between the pair of nanosheets, the first blocking layer including an edge barrier enhancing portion facing the sub-gate portion, and a second blocking layer, wherein the first blocking layer includes a portion that intermittently extends in the vertical direction.

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.

Abstract: An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region, an outer insulating spacer covering a sidewall of the gate line, a source/drain region on the fin-type active region, wherein the source/drain region includes a buffer layer including a portion in contact with the channel region and a portion in contact with the fin-type active region, the buffer layer including an edge buffer portion having a smaller thickness than other portions thereof at a position adjacent to the outer insulating spacer, a local buffer pattern including a wedge portion, the wedge portion filling a space defined by the edge buffer portion and the outer insulating spacer, and a main body layer in contact with each of the buffer layer and the local buffer pattern.

Abstract: A semiconductor device includes an active region, a plurality of channel layers disposed to be spaced apart from each other in a vertical direction on the active region, a gate structure extending in a second direction to intersect the active region and the plurality of channel layers and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers, and a contact plug connected to the source/drain region. The source/drain region includes a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers, second epitaxial layers disposed on the first epitaxial layer, each including impurities in a first concentration, and doping layers stacked alternately with the second epitaxial layers, each including the impurities in a second concentration higher than the first concentration.

Abstract: A semiconductor device includes; a gate structure intersecting an active region, and a plurality of channel layers, extending on the substrate in a second direction, and surrounding the plurality of channel layers; a source/drain region contacting the plurality of channel layers on at least one side of the gate structure and including a first semiconductor material with first impurities having a first conductivity type; and a lower structure in contact with the active region and below the source/drain region. The lower structure includes a first layer disposed on the active region and including an insulating material; a second layer disposed on the first layer and including a second semiconductor material; with an air gap defined by the first layer and the second layer, wherein the second semiconductor material of the second layer has no conductivity type or has a second conductivity type different from the first conductivity type.