Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.

Abstract: A memory device is provided. The memory device includes: a buffer memory; and a memory controller configured to: obtain map data and meta data for recovering the map data from at least one external storage device; store the map data and the meta data obtained from the at least one external storage device in the buffer memory, the buffer memory being allocated for the at least one external storage device; translate a logical address corresponding to the at least one external storage device into a physical address of the buffer memory; and send the map data and the meta data to the at least one external storage device in response to detecting a sudden power-off event.

Abstract: A method of operating a computing system which includes a plurality of storage devices, a memory device, and a switch, is provided. The method includes: providing a first mapping request including first metadata corresponding to first user data to the memory device through the switch, by a first storage device of the plurality of storage devices; identifying a first standard corresponding to the first metadata based on the first mapping request, by the memory device; and generating first map data indicating a relationship between a first physical block address and a first logical block address of the first user data based on the first standard, by the memory device.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: A method of wear leveling for a storage device or a memory device includes: receiving an inputted memory address; randomizing the inputted memory address to be a randomized memory address; and periodically reassigning the randomized memory address to be a different memory address.

Abstract: A method of wear leveling for a storage device or a memory device includes: receiving an inputted memory address; randomizing the inputted memory address to be a randomized memory address; and periodically reassigning the randomized memory address to be a different memory address.

Abstract: A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

Abstract: A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory.

Abstract: A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory.

Abstract: A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

Abstract: Example embodiments disclose a semiconductor device using resistive memory material layers and a method of driving the semiconductor device. The semiconductor device includes a plurality of memory cells. At least one memory cell includes a uni-polar variable resistor and a bi-polar variable resistor connected in series and configured to switch between low resistance states and high resistance states, respectively, according to an applied voltage.

Abstract: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

Abstract: In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.

Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: Example embodiments disclose a semiconductor device using resistive memory material layers and a method of driving the semiconductor device. The semiconductor device includes a plurality of memory cells. At least one memory cell includes a uni-polar variable resistor and a bi-polar variable resistor connected in series and configured to switch between low resistance states and high resistance states, respectively, according to an applied voltage.